參數(shù)資料
型號(hào)： AD8330ARQZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 29/32頁
文件大小： 0K
描述： IC AMP VGA 150MHZ LN LP 16QSOP
標(biāo)準(zhǔn)包裝： 2,500
放大器類型： 可變?cè)鲆?br>
電路數(shù)： 1
輸出類型： 差分，滿擺幅
轉(zhuǎn)換速率： 1500 V/µs
-3db帶寬： 150MHz
電流 - 輸入偏壓： 100nA
電流 - 電源： 20mA
電壓 - 電源，單路/雙路(±)： 2.7 V ~ 6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-QSOP
包裝： 帶卷 (TR)
配用： AD8330-EVALZ-ND - BOARD EVAL FOR AD8330
AD8330
Data Sheet
Rev. F | Page 6 of 32
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS
AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE GROUND PLANE.
PIN 1
INDICATOR
1
VPSI
2
INHI
3
INLO
4
MODE
11 OPHI
12 VPSO
10 OPLO
9
CMOP
5
V
DBS
6
CM
G
N
7
CO
M
8
VMA
G
15
OFS
T
16
E
NB
L
14
VPO
S
13
CNT
R
TOP VIEW
(Not to Scale)
AD8330
03217-
003
Figure 2. 16-Lead LFCSP Pin Configuration
1
S
O
P
V
T
S
F
O
16
2
R
T
N
C
L
B
N
E
15
3
O
S
P
V
I
S
P
V
14
4
I
H
P
O
I
H
N
I
13
5
O
L
P
O
L
N
I
12
6
P
O
M
C
E
D
O
M
11
7
G
A
M
V
S
B
D
V
10
8
M
O
C
N
G
M
C
9
AD8330
TOP VIEW
(Not to Scale)
03217-
004
Figure 3. 16-Lead QSOP Pin Configuration
Table 3. 16-Lead LFCSP Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VPSI
Positive Supply for Input Stages.
2
INHI
Differential Signal Input, Positive
Polarity.
3
INLO
Differential Signal Input, Negative
Polarity.
4
MODE
Logic Input: Selects Gain Slope.
High = gain up vs. V
DBS.
5
VDBS
Input for Linear-in-dB Gain Control
Voltage, V
DBS.
6
CMGN
Common Baseline for Gain Control
Interfaces.
7
COMM
Ground for Input and Gain Control Bias
Circuitry.
8
VMAG
Input for Gain/Amplitude Control, V
MAG.
9
CMOP
Ground for Output Stages.
10
OPLO
Differential Signal Output, Negative
Polarity.
11
OPHI
Differential Signal Output, Positive
Polarity.
12
VPSO
Positive Supply for Output Stages.
13
CNTR
Common-Mode Output Voltage Control.
14
VPOS
Positive Supply for Inner Stages.
15
OFST
Used in Offset Control Modes.
16
ENBL
Power Enable, Active High.
EPAD
Exposed Pad. It is recommended that
the pad be soldered to the ground
plane.
Table 4. 16-Lead QSOP Pin Function Descriptions
Pin No.
Mnemonic
Description
1
OFST
Used in Offset Control Modes.
2
ENBL
Power Enable, Active High.
3
VPSI
Positive Supply for Input Stages.
4
INHI
Differential Signal Input, Positive
Polarity.
5
INLO
Differential Signal Input, Negative
Polarity.
6
MODE
Logic Input: Selects Gain Slope.
High = gain up vs. V
DBS.
7
VDBS
Input for linear-in-dB Gain Control
Voltage, V
DBS.
8
CMGN
Common Baseline for Gain Control
Interfaces.
9
COMM
Ground for Input and Gain Control Bias
Circuitry.
10
VMAG
Input for Gain/Amplitude Control, V
MAG.
11
CMOP
Ground for Output Stages.
12
OPLO
Differential Signal Output, Negative
Polarity.
13
OPHI
Differential Signal Output, Positive
Polarity.
14
VPSO
Positive Supply for Output Stages.
15
CNTR
Common-Mode Output Voltage Control.
16
VPOS
Positive Supply for Inner Stages.
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