- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄5772 > AD8330ARQZ-RL (Analog Devices Inc)IC AMP VGA 150MHZ LN LP 16QSOP PDF資料下載
參數(shù)資料
| 型號： | AD8330ARQZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP VGA 150MHZ LN LP 16QSOP |
| 標準包裝： | 2,500 |
| 放大器類型： | 可變增益 |
| 電路數(shù)： | 1 |
| 輸出類型： | 差分，滿擺幅 |
| 轉換速率： | 1500 V/µs |
| -3db帶寬： | 150MHz |
| 電流 - 輸入偏壓： | 100nA |
| 電流 - 電源： | 20mA |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | AD8330-EVALZ-ND - BOARD EVAL FOR AD8330 |
第1頁第2頁第3頁第4頁第5頁第6頁當前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
Data Sheet
AD8330
Rev. F | Page 15 of 32
Normal Operating Conditions
To minimize confusion, normal operating conditions are
defined as follows:
The input pins are voltage driven (the source impedance is
assumed to be zero).
The output pins are open circuited (the load impedance is
assumed to be infinite).
Pin VMAG is unconnected setting up the output bias current
(IN in the four-transistor gain cell) to its nominal value.
Pin CMGN is grounded.
MODE is either tied to a logic high or left unconnected, to set
the up gain mode.
The effects of other operating conditions are considered
separately.
Throughout this data sheet, the end-to-end voltage gain for the
normal operating conditions is referred to as the basic gain.
Under these conditions, it runs from 0 dB when VDBS = 0 V
(where this voltage is more exactly measured with reference
to Pin CMGN, which is not necessarily tied to ground) up to
50 dB for VDBS = 1.5 V. The gain does not fold over when the
VDBS pin is driven below ground or above its nominal full-
scale value.
The input is accepted at the INHI/INLO differential port. These
pins are internally biased to roughly the midpoint of the supply,
VS (it is actually ~2.75 V for VS = 5 V, VDBS = 0 V, and 1.5 V for
VS = 3 V), but the AD8330 is able to accept a forced common-
mode value, from zero to VS, with certain limitations. This
interface provides good common-mode rejection up to high
frequencies (see Figure 16) and, thus, can be driven in either a
single-sided or differential manner. However, operation using a
differential drive is preferable, and this is assumed in the
specifications, unless otherwise stated.
The pin-to-pin input resistance is specified as 950 Ω ± 20%. The
driving-point impedance of the signal source can range from
zero up to values considerably in excess of this resistance, with a
corresponding variation in noise figure (see Figure 53). In most
cases, the input is coupled via two capacitors, chosen to provide
adequate low frequency transmission. This results in the minimum
input noise that increases when some other common-mode volt-
age is forced onto these pins. The short-circuit, input-referred
noise at maximum gain is approximately 5 nV/√Hz.
Output Pin OPHI and Output Pin OPLO operate at a common-
mode voltage at the midpoint of the supply, VS/2, within a few
millivolts. This ensures that an analog-to-digital converter
(ADC) attached to these outputs operates within the often
narrow range permitted by their design. When a common-
mode voltage other than VS/2 is required at this interface, it can
easily be forced by applying an externally provided voltage to
the output centering pin, CNTR. This voltage can run from zero
to the full supply, though the use of such extreme values leaves
only a small range for the differential output signal swing.
The differential impedance measured between OPHI and
OPLO is 150 Ω ± 20%. It follows that both the gain and the
full-scale voltage swing depend on the load impedance; both are
nominally halved when this is also 150 Ω. A fixed impedance
output interface, rather than an op amp style voltage-mode
output, is preferable in high speed applications because the
effects of complex reactive loads on the gain and phase can be
better controlled. The top end of the AD8330 ac response is
optimally flat for a 12 pF load on each pin, but this is not
critical, and the system remains stable for any value of load
capacitance including zero.
Another useful feature of this VGA in connection with the
driving of an ADC is that the peak output magnitude can be
precisely controlled by the voltage on Pin VMAG. Usually, this
voltage is internally preset to 500 mV, and the peak differential
unloaded output swing is ±2 V ± 3%. However, any voltage
from zero to at least 5 V can be applied to this pin to alter the
peak output in an exactly proportional way. Because either
output pin can swing rail-to-rail, which in practice means down
to at least 0.35 V and to within the same voltage below the
supply, the peak-to-peak output between these pins can be as
high as 10 V using VS = 6 V.
INHI
INLO
VDBS
VPSI
COMM
TRANSIMPEDANCE
OUTPUT STAGE
500
500
LINEAR-IN-dB
INTERFACE
MAGNITUDE
INTERFACE
5k
ROUT = 150
100A
VMAG
VPSO
OPHI
OPLO
ΔV = 0
12.65A–4mA OR
4mA–12.65A
COMM
VMAG
MODE
CNTR
ΔV = 0
O/P CM-MODE
NORMALLY
AT VP/2
CM MODE
FEEDBACK
VDBS
03217-
048
Figure 47. Schematic of Key Components
Linear-in-dB Gain Control (VDBS)
All Analog Devices, Inc., VGAs featuring a linear-in-dB gain
law, such as the X-AMP family, provide exact, constant gain
scaling over the fully specified gain range, and the deviation
from the ideal response is within a small fraction of a dB. For
the AD8330, the scaling of both of its gain interfaces is
substantially independent of process, supply voltage, or
temperature. The basic gain, GB, is simply
( )
mV
30
DBS
B
V
dB
G
=
(1)
where VDBS is in volts.
相關PDF資料 |
PDF描述 |
|---|---|
| 3-1445055-1 | CONN HEADER 3MM 11POS R/A TIN |
| 2020-42T-ALF | GAS DISCHARGE TUBE 3 POLE 360V |
| 170M5265 | FUSE 900A 690V 2KN/110 AR UC |
| AD713JRZ-16-REEL | IC OPAMP BIFET QUAD PREC 16SOIC |
| 77313-118-40LF | BERGSTIK |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD8330-EVAL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost, DC to 150 MHz Variable Gain Amplifier |
| AD8330-EVALZ | 功能描述:BOARD EVAL FOR AD8330 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 運算放大器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- |
| AD8331 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultralow Noise VGAs with Preamplifier and Programmable RIN |
| AD8331_06 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultralow Noise VGAs with Preamplifier and Programmable RIN |
| AD8331_10 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultralow Noise VGAs with Preamplifier and Programmable RIN |
發(fā)布緊急采購，3分鐘左右您將得到回復。