參數(shù)資料
型號： AD9117BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 30/52頁
文件大小： 0K
描述： IC DAC DUAL 14BIT LO PWR 40LFCSP
產(chǎn)品培訓模塊： Data Converter Fundamentals
DAC Architectures
設計資源： High CMRR Circuit for Converting Wideband Complementary DAC Outputs to Single-Ended Without Precision Resistors (CN0142)
標準包裝： 1
系列： TxDAC®
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 232mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤，CSP
供應商設備封裝： 40-LFCSP-VQ（6x6）
包裝： 托盤
輸出數(shù)目和類型： 4 電流，單極
采樣率（每秒）： 125M
產(chǎn)品目錄頁面： 785 (CN2011-ZH PDF)
AD9114/AD9115/AD9116/AD9117
Data Sheet
Rev. C | Page 36 of 52
SPI REGISTER DESCRIPTIONS
Reading these registers returns previously written values for all defined register bits, unless otherwise noted.
Table 14.
Register
Address
Bit
Name
Description
SPI Control
0x00
6
LSBFIRST
0 (default): MSB first per SPI standard.
1: LSB first per SPI standard.
Note that the user must always change the LSB/MSB order in single-byte
instructions to avoid erratic behavior due to bit order errors.
5
Reset
Executes software reset of SPI and controllers, reloads default register values,
except Register 0x00.
1: set software reset; write 0 on the next (or any following) cycle to release reset.
4
LNGINS
0 (default): the SPI instruction word uses a 5-bit address.
1: the SPI instruction word uses a 13-bit address.
Power Down
0x01
7
LDOOFF
0 (default): LDO voltage regulator on.
1: turns core LDO voltage regulator off.
6
LDOSTAT
0: indicates that the core LDO voltage regulator is off.
1 (default): indicates that the core LDO voltage regulator is on.
5
PWRDN
0 (default): all analog, digital circuitry and SPI logic are powered on.
1: powers down all analog and digital circuitry, except for SPI logic.
4
Q DACOFF
0 (default): turns on Q DAC output current.
1: turns off Q DAC output current.
3
I DACOFF
0 (default): turns on I DAC output current.
1: turns off I DAC output current.
2
QCLKOFF
0 (default): turns on Q DAC clock.
1: turns off Q DAC clock.
1
ICLKOFF
0 (default): turns on I DAC clock.
1: turns off I DAC clock.
0
EXTREF
0 (default): turns on internal voltage reference.
1: powers down the internal voltage reference (external reference required).
Data Control
0x02
7
TWOS
0 (default): Unsigned binary input data format.
1: twos complement input data format.
5
IFIRST
0: pairing of data—Q first of pair on data input pads.
1(default): pairing of data—I first of pair on data input pads (default).
4
IRISING
0: Q data latched on DCLKIO rising edge.
1(default): I data latched on DCLKIO rising edge (default).
3
SIMULBIT
0 (default): allows simultaneous input and output enable on DCLKIO.
1: disallows simultaneous input and output enable on DCLKIO.
2
DCI_EN
Controls the use of the DCLKIO pad for the data clock input.
0: data clock input disabled.
1(default): data clock input enabled.
1
DCOSGL
Controls the use of the DCLKIO pad for the data clock output.
0 (default): data clock output disabled.
1: data clock output enabled; regular strength driver.
0
DCODBL
Controls the use of the DCLKIO pad for the data clock output.
0 (default): DCODBL data clock output disabled.
1: DCODBL data clock output enabled; paralleled with DCOSGL for 2× drive current.
I DAC Gain
0x03
5:0
I DACGAIN[5:0]
DAC I fine gain adjustment; alters the full-scale current, as shown in Figure 99.
Default IDACGAIN = 0x00.
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