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參數(shù)資料
| 型號： | AD9117BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/52頁 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 14BIT LO PWR 40LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 設(shè)計資源： | High CMRR Circuit for Converting Wideband Complementary DAC Outputs to Single-Ended Without Precision Resistors (CN0142) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | TxDAC® |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 232mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 125M |
| 產(chǎn)品目錄頁面： | 785 (CN2011-ZH PDF) |
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Data Sheet
AD9114/AD9115/AD9116/AD9117
Rev. C | Page 49 of 52
Two registers are assigned to each DAC with 10 bits for the
actual DAC current to be generated, a 3-bit offset (and gain)
adjustment, a 2-bit current range adjustment, and an enable/
disable bit. Setting the QAUXOFS (Register 0x0A) and
IAUXOFS (Register 0x0C) bits to all 1s disables the respective
op amp and routes the DAC current directly to the respective
FSADJI/AUXI or FSADJQ/AUXQ pins. This is especially useful
when the loads to be driven are beyond the limited capability of
the on-chip amplifier.
When not enabled (QAUXEN or IAUXEN = 0), the respective
DAC output is in open circuit.
DAC-TO-MODULATOR INTERFACING
The auxiliary DACs can be used for local oscillator (LO)
cancellation when the DAC output is followed by a quadrature
modulator. This LO feedthrough is caused by the input referred
dc offset voltage of the quadrature modulator (and the DAC
output offset voltage mismatch) and can degrade system
performance. Typical DAC-to-quadrature modulator interfaces
are shown in Figure 107 and Figure 108, with the series resistor
value chosen to give an appropriate adjustment range. Figure 107
also shows external load resistors in use. Often, the input common-
mode voltage for the modulator is much higher than the output
compliance range of the DAC, so that ac coupling or a dc level
shift is necessary. If the required common-mode input voltage
on the quadrature modulator matches that of the DAC, the dc
blocking capacitors in Figure 107 can be removed and the on-chip
resistors can be connected.
AD9114/AD9115/
AD9116/AD9117
AUXDAC1
AD9114/AD9115/
AD9116/AD9117
I DAC
5k
TO
100k
50
OPTIONAL
PASSIVE
FILTERING
MODULATOR V+
QUADRATURE
MODULATOR
I OR Q
INPUTS
0.1F
07466-
268
Figure 107. Typical Use of Auxiliary DACs
Figure 108 shows a greatly simplified circuit that takes full
advantage of the internal components supplied in the DAC.
A low-pass or band-pass passive filter is recommended when
spurious signals from the DAC (distortion and DAC images) at the
quadrature modulator inputs can affect the system performance. In
the example shown in Figure 108, the filter must be able to pass dc
to properly bias the modulator. Placing the filter at the location
shown in Figure 107 and Figure 108 allows easy design of the filter,
because the source and load impedances can easily be designed
close to 50 for a 20 mA full-scale output. When the resistance
at the modulator inputs is known, an optimum value for the
series resistor can be calculated from the modulator input
offset voltage ratings.
AD9114/AD9115/
AD9116/AD9117
AUXDAC
AD9114/AD9115/
AD9116/AD9117
I OR Q DAC
5k
50
100
OPTIONAL
LOW- PASS
FILTERING
ADL5370
FAMILY
I OR Q INPUTS
07466-
269
Figure 108. Typical Use of Auxiliary DACs When DC Coupling to Quadrature
Modulator ADL537x Family
CORRECTING FOR NONIDEAL PERFORMANCE OF
QUADRATURE MODULATORS ON THE IF-TO-RF
CONVERSION
Analog quadrature modulators make it very easy to realize
single sideband radios. These DACs are most often used to make
radio transmitters, such as in cell phone towers. However, there
are several nonideal aspects of quadrature modulator performance.
Among these analog degradations are gain mismatch and LO
feedthrough.
Gain Mismatch
The gain in the real and imaginary signal paths of the quadrature
modulator may not be matched perfectly. This leads to less than
optimal image rejection because the cancellation of the negative
frequency image is less than perfect.
LO Feedthrough
The quadrature modulator has a finite dc referred offset, as well
as coupling from its LO port to the signal inputs. These can lead
to a significant spectral spur at the frequency of the quadrature
modulator LO.
The AD9114/AD9115/AD9116/AD9117 have the capability to
correct for both of these analog degradations. However, understand
that these degradations drift over temperature; therefore, if close to
optimal single sideband performance is desired, a scheme for
sensing these degradations over temperature and correcting
them may be necessary.
I/Q CHANNEL GAIN MATCHING
Fine gain matching is achieved by adjusting the values in the DAC
fine gain adjustment registers. For the I DAC, these values are in
the I DAC Gain register (Register 0x03, I DACGAIN[5:0]). For the
Q DAC, these values are in the Q DAC gain register (Register 0x06,
Q DACGAIN[5:0]). These are 6-bit values that cover ±2% of full
scale. To perform gain compensation by starting from the default
values of zero, raise the value of one of these registers a few steps
until it can be determined if the amplitude of the unwanted
image is increased or decreased. If the unwanted image increases in
amplitude, remove the step and try the same adjustment on the
other DAC control register. Iterate register changes until the
rejection cannot be improved further. If the fine gain adjustment
range is not sufficient to find a null (that is, the register goes full
scale with no null apparent), adjust the course gain settings of the
two DACs accordingly and try again. Variations on this simple
method are possible.
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| AD9117BCPZN | 功能描述:數(shù)模轉(zhuǎn)換器- DAC Dual 14B Low Power D-A Converter RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| AD9117BCPZNRL7 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC Dual Low Pwr 14-Bit RoHS:否 制造商:Analog Devices 轉(zhuǎn)換器數(shù)量:4 DAC 輸出端數(shù)量:4 轉(zhuǎn)換速率: 分辨率:12 bit 接口類型:Serial (I2C) 穩(wěn)定時間: 最大工作溫度:+ 105 C 安裝風(fēng)格: 封裝 / 箱體:TSSOP 封裝:Reel |
| AD9117BCPZRL7 | 功能描述:IC DAC DUAL 14BIT LO PWR 40LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9117-DPG2-EBZ | 功能描述:IC DAC DUAL 14BIT LO PWR 40LFCSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9117-EBZ | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9117, DUAL, 8-/10-/12-/14BIT LOW PWR DGTL-TO-A - Boxed Product (Development Kits) |
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