tS t
參數(shù)資料
型號: AD9222ABCPZRL7-50
廠商: Analog Devices Inc
文件頁數(shù): 29/60頁
文件大?。?/td> 0K
描述: IC ADC 12BIT SRL 50MSPS 64LFCSP
標準包裝: 750
位數(shù): 12
采樣率(每秒): 50M
數(shù)據(jù)接口: 串行,SPI?
轉換器數(shù)目: 8
功率耗散(最大): 760mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應商設備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 16 個單端,單極;8 個差分,單極
Data Sheet
AD9222
Rev. F | Page 35 of 60
DON’T CARE
SDIO
SCLK
CSB
tS
tDH
tHI
tCLK
tLO
tDS
tH
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
05967-
068
Figure 84. Serial Timing Details
Table 15. Serial Timing Definitions
Parameter
Timing (Minimum, ns)
Description
tDS
5
Setup time between the data and the rising edge of SCLK
tDH
2
Hold time between the data and the rising edge of SCLK
tCLK
40
Period of the clock
tS
5
Setup time between CSB and SCLK
tH
2
Hold time between CSB and SCLK
tHI
16
Minimum period that SCLK should be in a logic high state
tLO
16
Minimum period that SCLK should be in a logic low state
tEN_SDIO
10
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 84)
tDIS_SDIO
10
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising
edge (not shown in Figure 84)
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