參數(shù)資料
型號(hào)： AD9228ABCPZRL7-65
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/56頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT SPI/SRL 65M 48LFCSP
標(biāo)準(zhǔn)包裝： 750
位數(shù)： 12
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 510mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 8 個(gè)單端，單極；4 個(gè)差分，單極
AD9228
Data Sheet
Rev. E | Page 24 of 56
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (fA)
due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 57).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9228.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators are
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or another method), it
should be retimed by the original clock during the last step.
Application Note for more in-depth information about jitter
performance as it relates to ADCs.
1
10
100
1000
05
72
7-
03
8
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125 ps
0.25 ps
0.5 ps
1.0 ps
2.0 ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
RMS CLOCK JITTER REQUIREMENT
SN
R
(
d
B
)
Figure 57. Ideal SNR vs. Input Frequency and Jitter
Power Dissipation and Power-Down Mode
As shown in Figure 58 and Figure 59, the power dissipated by
the AD9228 is proportional to its sample rate. The digital power
dissipation does not vary significantly because it is determined
primarily by the DRVDD supply and bias current of the LVDS
output drivers.
10
20
15
30
35
25
40
CURRE
NT
(
m
A)
ENCODE (MSPS)
0
57
27
-08
9
180
220
200
240
300
340
320
360
260
280
0
20
40
100
140
120
180
160
60
80
DRVDD CURRENT
TOTAL POWER
AVDD CURRENT
P
O
WE
R
(
m
W)
Figure 58. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 40 MSPS
10
20
30
40
50
60
C
URRE
NT
(
m
A
)
P
O
WE
R
(
m
W)
ENCODE (MSPS)
05
72
7-
08
1
0
50
100
150
200
250
300
340
320
360
380
400
420
440
460
480
DRVDD CURRENT
TOTAL POWER
AVDD CURRENT
Figure 59. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 65 MSPS
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