- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1986 > AD9260ASZRL (Analog Devices Inc)IC ADC 16BIT 2.5MHZ 44MQFP PDF資料下載
參數(shù)資料
| 型號： | AD9260ASZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/44頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 2.5MHZ 44MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 585mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；1 個差分，單極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
AD9260
Rev. C | Page 23 of 44
THEORY OF OPERATION
The AD9260 utilizes a new analog-to-digital converter
architecture to combine sigma-delta techniques with a high
speed, pipelined A/D converter. This topology allows the
AD9260 to offer the high dynamic range associated with sigma-
delta converters while maintaining very wide input signal
bandwidth (1.25 MHz) at a very modest 8 oversampling ratio.
Figure 59 provides a block diagram of the AD9260. The
differential analog input is fed into a second order, multibit
sigma-delta modulator. This modulator features a 5-bit flash
quantizer and 5-bit feedback. In addition, a 12-bit pipelined
A/D quantizes the input to the 5-bit flash to greater accuracy. A
special digital modulation loop combines the output of the 12-
bit pipelined A/D with the delayed output of the 5-bit flash to
produce the equivalent response of a second order loop with a
12-bit quantizer and 12-bit feedback. The combination of a
second order loop and multibit feedback provides inherent
stability: the AD9260 is not prone to the idle tones or full-scale
idiosyncrasies sometimes associated with higher order single bit
sigma-delta modulators.
The output of this 12-bit modulator is fed into the digital
decimation filter. The voltage level on the MODE pin
establishes the configuration for the digital filter. The user may
bring the data out undecimated (at the clock rate), or at a
decimation factor of 2×, 4×, or a full 8×. The spectra for these
four cases are shown in Figure 11, Figure 12, Figure 13, and
Figure 14, all for a 100 kHz full-scale input and 20 MHz clock.
The spectra of the undecimated output clearly shows the second
order shaping characteristic of the quantization noise as it rises
at frequencies above 1.25 MHz.
The on-chip decimation filter provides excellent stopband
rejection to suppress any stray input signal between 1.25 MHz
and 18.75 MHz, substantially easing the requirements on any
antialiasing filter for the analog input path. The decimation
filters are integrated with symmetric FIR filter structures,
providing a linear phase response and excellent passband
flatness. The digital output driver register of the AD9260
features both READ and CHIP SELECT pins to allow easy
interfacing. The digital supply of the AD9260 is designed to
operate over a 2.7 V to 5.25 V supply range, though 3 V supplies
are recommended to minimize digital noise on the board. A
DATA AVAILABLE pin allows the user to easily synchronize to
the converter’s decimated output data rate. OUT-OF-RANGE
(OTR) indication is given for an overflow in the pipelined A/D
converter or digital filters. A RESETB function is provided to
synchronize the converter’s decimated data and clear any
overflow condition in the analog integrators.
An on-chip reference and reference buffer are included on the
AD9260. The reference can be configured in either a 2.5 V
mode (providing a 4 V p-p differential input full scale), a 1 V
mode (providing a 1.6 V p-p differential input full scale), or
programmed with an external resistor divider to provide any
voltage level between 1 V and 2.5 V. However, optimum noise
and distortion performance for the AD9260 can only be achieved
with a 2.5 V reference, as shown in Figure 52.
For users who want to operate the part at reduced clock
frequencies, the bias current of the AD9260 is designed to be
scalable. This scaling is accomplished through use of the proper
external resistor tied to the BIAS pin: the power can be reduced
roughly proportionately to clock frequency by as much as 75%
(for clock rates of 5 MHz). Refer to Figure 47 to Figure 49 and
performance tradeoffs.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9262BCPZ-10 | IC ADC 16BIT 10MHZ 64LFCSP |
| AD9266BCPZRL7-20 | IC ADC 16BIT 20MSPS 32LFCSP |
| AD9269BCPZRL7-20 | IC ADC 16BIT 20MSPS DL 64LFCSP |
| AD9271BSVZ-40 | IC ADC OCT 12BIT 40MSPS 100-TQFP |
| AD9280ARSRL | IC ADC 8BIT CMOS 32MSPS 28-SSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9260EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate |
| AD9260-EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9260 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9260 - Bulk |
| AD9261-10EBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 16Bit 10 MHz Sigma Delta ADC EB RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| AD9261BCPZ-10 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16Bit 10 MHz Sigma Delta ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
| AD9261BCPZRL7-10 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16Bit 10 MHz Sigma Delta ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。