- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1986 > AD9260ASZRL (Analog Devices Inc)IC ADC 16BIT 2.5MHZ 44MQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9260ASZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 2.5MHZ 44MQFP |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 585mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)單端，單極；1 個(gè)差分，單極 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當(dāng)前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
AD9260
Rev. C | Page 34 of 44
A/D with a total rms jitter of 15 ps, the SNR performance of the
A/D will be limited to 86.5 dB.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9260. In fact, the CLK input buffer is internally powered
from the AD9260’s analog supply, AVDD. Thus the CLK
logic high and low input voltage levels are +3.5 V and
+1.0 V, respectively.
Supplies for clock drivers should be separated from the A/D
output driver supplies to avoid modulating the clock signal with
digital noise. Low jitter crystal controlled oscillators make the
best clock sources. If the clock is generated from another type of
source (by gating, dividing, or other method), it should be
retimed by the original clock at the last step.
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are
recommended to provide optimal grounding and power
schemes. The use of ground and power planes offers
distinct advantages:
1.
The minimization of the loop area encompassed by a signal
and its return path.
2.
The minimization of the impedance associated with
ground and power paths.
3.
The inherent distributed capacitor formed by the power
plane, PCB insulation, and ground plane.
These characteristics result in both a reduction of
electromagnetic interference (EMI) and an overall
improvement in performance.
It is important to design a layout that prevents noise from
coupling onto the input signal. Digital signals should not be run
in parallel with input signal traces and should be routed away
from the input circuitry. While the AD9260 features separate
analog and digital ground pins, it should be treated as an analog
component. The AVSS, DVSS and DRVSS pins must be joined
together directly under the AD9260. A solid ground plane under
the A/D is acceptable if the power and ground return currents
are managed carefully. Alternatively, the ground plane under
the A/D may contain serrations to steer currents in predictable
directions where cross-coupling between analog and digital
would otherwise be unavoidable. The AD9260/EB ground
layout, shown in Figure 83, depicts the serrated type of
arrangement. The analog and digital grounds are connected by
a jumper below the A/D.
Analog and Digital Supply Decoupling
The AD9260 features separate analog, digital, and driver supply
and ground pins, helping to minimize digital corruption of
sensitive analog signals.
Figure 73 shows the power supply rejection ratio vs. frequency
for a 200 mV p-p ripple applied to AVDD, DVDD, and
DAVDD.
40
45
50
55
60
65
70
75
80
85
90
P
S
RR
(dBFS
)
FREQUENCY (kHz)
101
0102
103
104
00581-C-073
AVDD
DVDD AND DRVDD
Figure 73. AD9260 PSRR vs. Frequency (8x Mode)
In general, AVDD, the analog supply, should be decoupled to
AVSS, the analog common, as close to the chip as physically
possible. Figure 74 shows the recommended decoupling for the
analog supplies; 0.1 F ceramic chip capacitors should provide
adequately low impedance over a wide frequency range. Note
that the AVDD and AVSS pins are co-located on the AD9260 to
simplify the layout of the decoupling capacitors and provide the
shortest possible PCB trace lengths. The AD9260/EB power
plane layout, shown in Figure 84 depicts a typical arrangement
using a multilayer PCB.
00581-C-074
AVDD
AVSS
AD9260
AVDD
AVSS
0.1
F
0.1
F
0.1
F
AVDD
AVSS
4
3
28
29
38
44
Figure 74. Analog Supply Decoupling
The digital activity on the AD9260 chip falls into two general
categories: digital logic and output drivers. The internal digital
logic draws surges of current, mainly during the clock
transitions. The output drivers draw large current impulses
while the output bits are changing. The size and duration of
these currents are a function of the load on the output bits: large
capacitive loads are to be avoided. Note that the digital logic of
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9262BCPZ-10 | IC ADC 16BIT 10MHZ 64LFCSP |
| AD9266BCPZRL7-20 | IC ADC 16BIT 20MSPS 32LFCSP |
| AD9269BCPZRL7-20 | IC ADC 16BIT 20MSPS DL 64LFCSP |
| AD9271BSVZ-40 | IC ADC OCT 12BIT 40MSPS 100-TQFP |
| AD9280ARSRL | IC ADC 8BIT CMOS 32MSPS 28-SSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9260EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate |
| AD9260-EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9260 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9260 - Bulk |
| AD9261-10EBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 16Bit 10 MHz Sigma Delta ADC EB RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評(píng)估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| AD9261BCPZ-10 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16Bit 10 MHz Sigma Delta ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
| AD9261BCPZRL7-10 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16Bit 10 MHz Sigma Delta ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風(fēng)格: 封裝 / 箱體: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。