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參數資料
型號: AD9262BCPZRL7
廠商: Analog Devices Inc
文件頁數: 14/32頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 2.5MHZ 64LFCSP
設計資源: Interfacing ADL5382 to AD9262 as an RF-to-Bits Solution (CN0062)
標準包裝: 750
位數: 16
采樣率(每秒): 160M
數據接口: 串行,SPI?
轉換器數目: 2
功率耗散(最大): 640mW
電壓電源: 模擬和數字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應商設備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數目和類型: 2 個單端,雙極;1 個差分,單極
AD9262
Rev. A | Page 21 of 32
DIGITAL ENGINE
Bandwidth Selection
The digital engine (see Figure 54) selects the decimation signal
bandwidth by cascading third-order sinc (sinc3) decimate-by-2
filters. For a 10 MHz signal band, no filters are cascaded; for a
5 MHz signal band, a single filter is used; and for a 2.5 MHz
signal band, the 5 MHz filter is cascaded with a second filter.
Depending on the signal bandwidth, this drops the data rate
into the fixed decimation filter. As a result, lower signal bandwidth
options result in lower power. Bandwidth selection is determined
by setting Serial Register 0x0F[6:5]. Table 13 summarizes the
available bandwidth options.
Table 13. Output Bandwidth Options
BW[1:0]
AD9262BCPZ
AD9262BCPZ-5
AD9262BCPZ-10
0x0
2.5 MHz
5 MHz
10 MHz
0x1
2.5 MHz
5 MHz
0x2
2.5 MHz
0x3
2.5 MHz
Decimation Filters
The fixed decimation filters reduce the sample rate from 640 MSPS
to 40 MSPS. A fixed frequency low-pass filter is used to define
the signal band. This filter incorporates magnitude equalization
for the droop of the preceding sinc decimation filters and the
sinc filters of the sample rate converter. Table 14 and Table 15
detail the coefficients for the DEC4 and LPF/EQZ filters. Sinc filter
implementation for all sinc filters is standard.
Table 14. DEC4 Filter Coefficients
Coefficient
Number
Coefficient
Number
Coefficient
C0, C22
21
C6, C16
1121
C1, C21
0
C7, C15
0
C2, C20
122
C8, C14
2796
C3, C19
0
C9, C13
0
C4, C18
418
C10, C12
10,184
C5, C17
0
C11
16,384
Table 15. LPF/EQZ Filter Coefficients
Coefficient
Number
Coefficient
Number
Coefficient
C0, C62
17
C16, C46
694
C1, C61
31
C17, C45
744
C2, C60
15
C18, C44
677
C3, C59
52
C19, C43
1271
C4, C58
36
C20, C42
450
C5, C57
78
C21, C41
1909
C6, C56
84
C22, C40
103
C7, C55
98
C23, C39
2612
C8, C54
170
C24, C38
1147
C9, C53
97
C25, C37
3326
C10, C52
291
C26, C36
3022
C11, C51
42
C27, C35
4051
C12, C50
441
C28, C34
6870
C13, C49
98
C29, C33
5305
C14, C48
592
C30, C32
21,141
C15, C47
353
C31
38,956
10MHz
5MHz
2.5MHz
10MHz
5MHz
2.5MHz
DEC01
4
DEC02
SINC3 2
SINC4 2
SINC6 2
FIR
HB 2
DEC1
DEC2
DEC3
DEC4
LPF/EQZ
DECIMATION FILTERS
BANDWIDTH SELECTION
HB 2
INT1
HB 2
INT2
SINC5 4
INT3
2
5MHz
2.5MHz
10MHz
SINC5 8
INT4
NCO
SAMPLE RATE CONVERTER
Σ-Δ
OUTPUT
16
DATA
OUTPUT
0
7
772
-05
0
Figure 54. Digital Engine
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