參數(shù)資料
型號: AD9262BCPZRL7
廠商: Analog Devices Inc
文件頁數(shù): 32/32頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 2.5MHZ 64LFCSP
設(shè)計(jì)資源: Interfacing ADL5382 to AD9262 as an RF-to-Bits Solution (CN0062)
標(biāo)準(zhǔn)包裝: 750
位數(shù): 16
采樣率(每秒): 160M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 640mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個(gè)單端,雙極;1 個(gè)差分,單極
AD9262
Rev. A | Page 9 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR THE
LFCSP PACKAGE. SOLDERING THE EXPOSED PADDLE TO THE PCB
INCREASES THE RELIABILITY OF THE SOLDER JOINTS, MAXIMIZING
THE THERMAL CAPACITY OF THE PACKAGE.
PIN 1
INDICATOR
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D1
1B
D12B
D13B
D14B
D15B
OR
B
DR
VD
D
DG
ND
DV
DD
DC
O
D0
A
D1
A
D2
A
D3
A
D4
A
D5
A
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
CL
K
+
CG
ND
AG
ND
AV
D
VI
N
–B
VI
N
+
B
AV
D
CF
IL
T
VR
E
F
AV
D
VI
N
A
VI
N
+
A
AV
D
AG
ND
RE
S
E
T
CS
B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK–
CVDD
D0B
D1B
D2B
DVDD
DGND
DRVDD
D3B
D4B
D5B
D6B
D7B
D8B
D9B
D10B
SCLK
SDIO
ORA
D15A
D14A
DVDD
DGND
DRVDD
D13A
D12A
D11A
D10A
D9A
D8A
D7A
D6A
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9262
CMOS OUTPUTS
TOP VIEW
(Not to Scale)
07
77
2-
00
3
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CLK
Clock Input ().
2
CVDD
Clock Supply (1.8 V).
3 to 5, 9 to 21
D0B to D15B
Channel B Data Output Pins. D0B is the LSB and D15B is the MSB.
6, 25, 43
DVDD
Digital Supply (1.8 V).
7, 24, 42
DGND
Digital Ground.
8, 23, 41
DRVDD
Digital Output Driver Supply (1.8 V to 3.3 V).
22
ORB
Channel B Overrange Indicator.
26
DCO
Data Clock Output.
27 to 40, 44, 45
D0A to D15A
Channel A Data Output Pins. D0A is the LSB and D15A is the MSB.
46
ORA
Channel A Overrange Indicator.
47
SDIO
Serial Port Interface Data Input/Output.
48
SCLK
Serial Port Interface Clock.
49
CSB
Serial Port Interface Chip Select Active Low.
50
RESET
Chip Reset.
51, 62
AGND
Analog Ground.
52, 55, 58, 61
AVDD
Analog Supply (1.8 V).
53
VIN+A
Channel A Analog Input (+).
54
VINA
Channel A Analog Input ().
56
VREF
Voltage Reference Input.
57
CFILT
Noise Limiting Filter Capacitor.
59
VIN+B
Channel B Analog Input (+).
60
VINB
Channel B Analog Input ().
63
CGND
Clock Ground.
64
CLK+
Clock Input (+).
65 (EPAD)
Exposed pad (EPAD)
Analog Ground. (Pin 65 is the exposed thermal pad on the bottom of the package.) The
exposed pad must be soldered to ground.
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