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參數(shù)資料
| 型號： | AD9279-80KITZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/44頁 |
| 文件大小： | 0K |
| 描述： | KIT EVALUATION FOR AD9279 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 8 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 串行 |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9279 |
| 已供物品： | 板 |
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AD9279
Rev. 0 | Page 39 of 44
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map register table has eight bit loca-
tions. The memory map is roughly divided into three sections:
the chip configuration register map (Address 0x00 to Address 0x02),
the device index and transfer register map (Address 0x04 to
Address 0xFF), and the program register map (Address 0x08
to Address 0x2D).
The leftmost column of the memory map indicates the register
address, and the default value is shown in the second rightmost
column. The Bit 7 (MSB) column is the start of the default
hexadecimal value given. For example, Address 0x09, the clock
register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 =
0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1,
or 0000 0001 in binary. This setting is the default for the duty
cycle stabilizer in the on condition. By writing a 0 to Bit 0 of this
address, followed by 0x01 in Register 0xFF (the transfer bit), the
duty cycle stabilizer is turned off. It is important to follow each
writing sequence with a transfer bit to update the SPI registers.
All registers except Register 0x00, Register 0x04, Register 0x05,
and Register 0xFF are buffered with a master slave latch and
require writing to the transfer bit. For more information on this
and other functions, consult the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
RESERVED LOCATIONS
Undefined memory locations should not be written to except
when writing the default values suggested in this data sheet.
Addresses that have values marked as 0 should be considered
reserved and have a 0 written into their registers during power-up.
DEFAULT VALUES
After a reset, critical registers are automatically loaded with
default values. These values are indicated in Table 19, where an
X refers to an undefined feature.
LOGIC LEVELS
An explanation of various registers follows: “bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “bit is cleared” is synonymous with “bit is set
to Logic 0” or “writing Logic 0 for the bit.”
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