參數(shù)資料
型號: AD9279-80KITZ
廠商: Analog Devices Inc
文件頁數(shù): 41/44頁
文件大?。?/td> 0K
描述: KIT EVALUATION FOR AD9279
標準包裝: 1
ADC 的數(shù)量: 8
位數(shù): 12
采樣率(每秒): 80M
數(shù)據(jù)接口: 串行
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9279
已供物品:
AD9279
Rev. 0 | Page 6 of 44
DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature, unless otherwise noted.
Table 2.
Parameter1
Temperature
Min
Typ
Max
Unit
CLOCK INPUTS (CLK+, CLK)
Logic Compliance
CMOS/LVDS/LVPECL
Differential Input Voltage2
Full
250
mV p-p
Input Common-Mode Voltage
Full
1.2
V
Input Resistance (Differential)
25°C
20
Input Capacitance
25°C
1.5
pF
CW 4LO INPUTS (4LO+, 4LO)
Logic Compliance
CMOS/LVDS/LVPECL
Differential Input Voltage2
Full
250
mV p-p
Input Common-Mode Voltage
Full
1.2
V
Input Resistance (Differential)
25°C
20
Input Capacitance
25°C
1.5
pF
LOGIC INPUTS (PDWN, STBY, SCLK, SDIO)
Logic 1 Voltage
Full
1.2
AVDD1 + 0.3
V
Logic 0 Voltage
Full
0.3
V
Input Resistance
25°C
30
Input Capacitance
25°C
0.5
pF
LOGIC INPUTS (RESET)
Logic 1 Voltage
Full
1.2
AVDD2 + 0.3
V
Logic 0 Voltage
Full
0.3
V
Input Resistance
25°C
30
Input Capacitance
25°C
0.5
pF
LOGIC INPUT (CSB)
Logic 1 Voltage
Full
1.2
AVDD1 + 0.3
V
Logic 0 Voltage
Full
0.3
V
Input Resistance
25°C
70
Input Capacitance
25°C
0.5
pF
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA)
Full
1.79
V
Logic 0 Voltage (IOL = 50 μA)
Full
0.05
V
DIGITAL OUTPUTS (DOUTx+, DOUTx), (ANSI-644)
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
247
454
mV
Output Offset Voltage (VOS)
Full
1.125
1.375
V
Output Coding (Default)
Offset binary
DIGITAL OUTPUTS (DOUTx+, DOUTx),
(LOW POWER, REDUCED SIGNAL OPTION)
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
150
250
mV
Output Offset Voltage (VOS)
Full
1.10
1.30
V
Output Coding (Default)
Offset binary
LOGIC OUTPUT (GPO0/GPO1/GPO2/GPO3)
Logic 0 Voltage (IOL = 50 μA)
Full
0.05
V
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 Specified for LVDS and LVPECL only.
3 Specified for 13 SDIO pins sharing the same connection.
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