參數(shù)資料
型號(hào)： AD9279-80KITZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 36/44頁(yè)
文件大小： 0K
描述： KIT EVALUATION FOR AD9279
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 8
位數(shù)： 12
采樣率（每秒）： 80M
數(shù)據(jù)接口： 串行
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9279
已供物品： 板
AD9279
Rev. 0 | Page 41 of 44
Addr.
(Hex)
Register Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
Comments
0x0F
FLEX_CHANNEL_
INPUT
Filter cutoff frequency control
0000 = 1.3 × 1/3 × fSAMPLE
0001 = 1.2 × 1/3 × fSAMPLE
0010 = 1.1 × 1/3 × fSAMPLE
0011 = 1.0 × 1/3 × fSAMPLE (default)
0100 = 0.9 × 1/3 × fSAMPLE
0101 = 0.8 × 1/3 × fSAMPLE
0110 = 0.7 × 1/3 × fSAMPLE
1000 = 1.3 × 1/4.5 × fSAMPLE
1001 = 1.2 × 1/4.5 × fSAMPLE
1010 = 1.1 × 1/4.5 × fSAMPLE
1011 = 1.0 × 1/4.5 × fSAMPLE
1100 = 0.9 × 1/4.5 × fSAMPLE
1101 = 0.8 × 1/4.5 × fSAMPLE
1110 = 0.7 × 1/4.5 × fSAMPLE
X
0x30
Antialiasing filter
cutoff (global).
0x10
FLEX_OFFSET
X
1
0
0x20
Reserved.
0x11
FLEX_GAIN
X
PGA gain
00 = 21 dB
01 = 24 dB (default)
10 = 27 dB
11 = 30 dB
LNA gain
00 = 15.6 dB
01 = 17.9 dB
10 = 21.3 dB
(default)
0x06
LNA and PGA gain
adjustment
(global).
0x12
BIAS_CURRENT
X
1
X
LNA bias
00 = high
01 = mid-high
(default)
10 = mid-low
11 = low
0x09
LNA bias current
adjustment
(global).
0x14
OUTPUT_MODE
X
0 = LVDS
ANSI-644
(default)
1 = LVDS
low power,
(IEEE
1596.3
similar)
X
Output
invert
enable
1 = on
0 = off
(default)
Data format select
00 = offset binary
(default)
01 = twos
complement
0x00
Configures the
outputs and the
format of the data
(Bits[7:3] and
Bits[1:0] are global;
Bit 2 is local).
0x15
OUTPUT_ADJUST
X
Output driver
termination
00 = none (default)
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
X
DCO±
and
FCO±
2× drive
strength
1 = on
0 = off
(default)
0x00
Determines LVDS
or other output
properties.
Primarily functions
to set the LVDS
span and
common-mode
levels in place of
an external resistor
(Bits[7:1] are global;
Bit 0 is local).
0x16
OUTPUT_PHASE
X
Output clock phase adjust
0000 = 0° relative to data edge
0001 = 60° relative to data edge
0010 = 120° relative to data edge
0011 = 180° relative to data edge (default)
0100 = reserved
0101 = 300° relative to data edge
0110 = 360° relative to data edge
0111 = reserved
1000 = 480° relative to data edge
1001 = 540° relative to data edge
1010 = 600° relative to data edge
1011 to 1111 = 660° relative to data edge
0x03
On devices that
use global clock
divide, deter-
mines which
phase of the
divider output is
used to supply
the output clock.
Internal latching
is unaffected.
(global)
0x18
FLEX_VREF
X
0 =
internal
reference
1 =
external
reference
X
1
0x03
Select internal
reference
(recommended
default) or
external reference
(global).
0x19
USER_PATT1_LSB
B7
B6
B5
B4
B3
B2
B1
B0
0x00
User-Defined
Pattern 1, LSB
(global).
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