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參數(shù)資料
| 型號： | AD9287BCPZRL7-100 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/52頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT QUAD 100MSPS 48LFCSP |
| 產(chǎn)品變化通告： | Product Discontinuation 12/Mar/2010 |
| 標準包裝： | 1 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 100M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 4 |
| 功率耗散（最大）： | 562mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 8 個單端，單極；4 個差分，單極 |
| 配用： | AD9287-100EBZ-ND - BOARD EVALUATION AD9287 |
| 其它名稱： | AD9287BCPZRL7-100DKR |
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Data Sheet
AD9287
Rev. E | Page 23 of 52
By asserting the PDWN pin high, the AD9287 is placed into
power-down mode. In this state, the ADC typically dissipates
3 mW. During power-down, the LVDS output drivers are placed
into a high impedance state. If any of the SPI features are changed
before the power-down feature is enabled, the chip continues to
function after PDWN is pulled low without requiring a reset. The
AD9287 returns to normal operating mode when the PDWN pin
is pulled low. This pin is both 1.8 V and 3.3 V tolerant.
In power-down mode, low power dissipation is achieved by
shutting down the reference, reference buffer, PLL, and biasing
networks. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in the power-down
mode: shorter cycles result in proportionally shorter wake-up
times. With the recommended 0.1 μF and 2.2 μF decoupling
capacitors on REFT and REFB, approximately 1 sec is required
to fully discharge the reference buffer decoupling capacitors and
approximately 375 μs is required to restore full operation.
There are several other power-down options available when
using the SPI. The user can individually power down each
channel or put the entire device into standby mode. The latter
option allows the user to keep the internal PLL powered when
fast wake-up times (~600 ns) are required. See the Memory
Map section for more details on using these features.
Digital Outputs and Timing
The AD9287 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option (similar to the IEEE 1596.3 standard) via the
SDIO/ODM pin or SPI. The LVDS standard can further reduce the
overall power dissipation of the device by approximately 17 mW.
section for more information. The LVDS driver current is derived
on-chip and sets the output current at each output equal to a
nominal 3.5 mA. A 100 Ω differential termination resistor placed at
the LVDS receiver inputs results in a nominal 350 mV swing at
the receiver.
The AD9287 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
placed as close to the receiver as possible. If there is no far-end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is recom-
mended that each trace length be less than 24 inches and that
the differential output traces be close together and at equal
lengths. An example of the FCO and data stream with proper
trace length and position is shown in Figure 49.
05
96
6-
0
56
CH1 500mV/DIV = FCO
CH2 500mV/DIV = DATA
CH3 500mV/DIV = DCO
2.5ns/DIV
Figure 49. LVDS Output Timing Example in ANSI-644 Mode (Default)
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths less than 24 inches on standard FR-4 material is
shown in Figure 50. Figure 51 shows an example of trace lengths
exceeding 24 inches on standard FR-4 material. Notice that the
TIE jitter histogram reflects the decrease of the data eye opening
as the edge deviates from the ideal position. It is the user’s respon-
sibility to determine if the waveforms meet the timing budget of
the design when the trace lengths exceed 24 inches. Additional SPI
options allow the user to further increase the internal termination
(increasing the current) of all four outputs in order to drive longer
trace lengths (see Figure 52). Even though this produces sharper
rise and fall times on the data edges and is less prone to bit errors,
the power dissipation of the DRVDD supply increases when this
option is used. In addition, notice in Figure 52 that the histogram
is improved compared with that shown in Figure 51. See the
Memory Map section for more details.
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