參數(shù)資料
型號(hào): AD9287BCPZRL7-100
廠商: Analog Devices Inc
文件頁(yè)數(shù): 36/52頁(yè)
文件大?。?/td> 0K
描述: IC ADC 8BIT QUAD 100MSPS 48LFCSP
產(chǎn)品變化通告: Product Discontinuation 12/Mar/2010
標(biāo)準(zhǔn)包裝: 1
位數(shù): 8
采樣率(每秒): 100M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 4
功率耗散(最大): 562mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類(lèi)型: 8 個(gè)單端,單極;4 個(gè)差分,單極
配用: AD9287-100EBZ-ND - BOARD EVALUATION AD9287
其它名稱: AD9287BCPZRL7-100DKR
Data Sheet
AD9287
Rev. E | Page 41 of 52
MOD
EPI
N
POS
ITIVE
GAIN
SLOP
E=
0V
TO1
.0V
NE
GATIV
EGA
INS
LOPE
=2
.25
VTO
5.0
V
HILO
PIN
HIG
AIN
RANGE
=2.
25VT
O5.
0V
LO
GAI
NRANG
E=
0VT
O1.
0V
R414
10k
L
410
120n
H
C420
0.018
F
C415
0.
018
F
R415
274
C410
0.
1
F
C425
0.
1
F
C423
0.
1
F
C424
0.
1
F
L
409
120n
H
C418
22p
F
C417
0.
1
F
C416
0.
1
F
C414
0.
1
F
R417
10kΩ
C421
22p
F
C419
0.
1
F
C422
0.
1
F
INH2
INH1
AVDD_5V
C426
10
F
C413
10
F
OP
TIO
NALV
GA
DRIV
ECI
RCUIT
FO
RCHANNE
LA
ANDCHANNE
LB
C409
0.
1
F
R411
10kΩ
R412
10kΩ DNP
C403
DNP
L
404
0
R403
DNP
L
408
0
24
17
20
23
18
22
19
21
R404
DNP
L
406
0
L
405
0
L
402
0
L
403
0
L
407
0
C408
0.
1
F
C407
0.
1
F
C406
0.
1
F
C405
0.
1
F
R410
187
R409
187Ω
R408
187Ω
R407
187Ω
C402
DNP
L
401
0
C401
DNP
R405
374Ω
R406
374Ω
CH_A
CH_B
CH_A
AVDD_5V
C404
DNP
R401
DNP
R402
DNP
31
10
26
25
14
27
3
6
4
5
1
8
32
9
15
16
VG
28
13
29
12
30
11
2
7
CO
M
1
CO
M
2
E
NBL
E
NBV
GA
IN
H
ILO
INH1
INH2
LM
D1
LM
D2
LON1
LON2
LOP
1
LOP
2
M
O
DE
NC
RCL
M
P
VC
M1
VC
M2
V
IN1
V
IN2
VI
P1
VI
P2
VO
H1
VO
H2
VOL1
VOL2
VPS1
VPS2
VPSV
AD8332
U401
COM
M
COM
M
R413
10k DNP
R424
10k DNP
C412
0.
1
F
C411
1000p
F
RCLAM
PP
IN
HILO
PIN
=LO
50
mV
HIL
OP
IN
=H
75mV
PO
WE
RDO
WN
ENABL
E
(0V
TO
1V
=D
ISA
BL
EPO
WER
)
R416
274
POPU
LA
TE
L401
TO
L408
WIT
H
0
R
ESIST
OR
SO
RD
ESIG
N
YOUR
OW
NF
ILT
ER.
Y1
V
CC
Y2
A2
G
ND
A1
S
P
IC
IR
C
U
ITR
Y
FR
OM
FIFO
S
DI
O
_O
DM
AV
DD_DUT
R431
1k
R432
1k
R433
1k
AV
DD_3.
3V
1
2
3
4
5
6
NC7W
Z
07
U403
R425
10k
AV
DD_DUT
RE
S
E
T
/RE
P
RO
G
RAM
1
2
3
4
S
401
+
3.
3V
=
NO
RM
AL
O
P
E
RAT
IO
N
=
AV
DD_3.
3V
+
5V
=
P
RO
G
RAM
M
ING
=
AV
DD_5V
AV
DD_5V
AV
DD_3.
3V
J402
C427
0.
1
F
R418
4.75k
P
IC12F
629
R419
261Ω
4
3
1
2
5
6
8
7
U402
CR401
G
P0
G
P1
G
P2
G
P4
G
P5
V
DD
VSS
M
CL
R/
G
P3
R
EMO
VE
W
H
EN
U
SI
N
G
O
R
P
RO
G
RAM
M
ING
P
IC
(
U402)
R427
0
R420
0
R428
0
R426
0
SDO
_CHA
SDI
_CHA
SCL
K_CHA
CSB1_CHA
C429
0.
1
F
S
CL
K_DT
P
CS
B_DUT
AV
DD_DUT
Y1
V
CC
Y2
A2
G
ND
A1
1
2
3
4
5
6
U404
R430
10k
R429
10k
NC7W
Z
16
C428
0.
1
F
PIC
PRO
GRAM
MING
HEADE
R
MC
LR/GP
3
GP0
GP1
PICV
CC
MC
LR/GP
3
GP0
GP1
PICV
CC
9
7
5
3
1
10
8
6
4
2
J401
E
401
R421
,DNP
R423
,DNP
R422
,DNP
OPTION
AL
DNP
:DO
NO
T
P
O
P
UL
AT
E
05966-018
Figure 65. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit (Continued)
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