參數(shù)資料
型號(hào)： AD9287BCPZRL7-100
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/52頁(yè)
文件大小： 0K
描述： IC ADC 8BIT QUAD 100MSPS 48LFCSP
產(chǎn)品變化通告： Product Discontinuation 12/Mar/2010
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 8
采樣率（每秒）： 100M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
功率耗散（最大）： 562mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型： 8 個(gè)單端，單極；4 個(gè)差分，單極
配用： AD9287-100EBZ-ND - BOARD EVALUATION AD9287
其它名稱： AD9287BCPZRL7-100DKR
AD9287
Data Sheet
Rev. E | Page 24 of 52
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
500
–500
0
–1.0ns
–0.5ns
0ns
0.5ns
1.0ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(V)
EYE: ALL BITS
ULS: 10000/15600
05966-
043
100
50
0
–100ps
0ps
100ps
Figure 50. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Less than 24 Inches on Standard FR-4, External 100 Far Termination Only
200
–200
0
–1.0ns
–0.5ns
0ns
0.5ns
1.0ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(V)
EYE: ALL BITS
ULS: 9600/15600
05966-
044
100
50
0
–150ps
–100ps
–50ps
0ps
50ps
100ps
150ps
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
Figure 51. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, External 100 Far Termination Only
200
400
–200
–400
0
–1.0ns
–0.5ns
0ns
0.5ns
1.0ns
EYE
D
IA
G
R
A
M
VO
L
T
A
G
E
(V)
EYE: ALL BITS
ULS: 9599/15599
05966-
042
100
50
0
–150ps
–100ps
–50ps
0ps
50ps
100ps
150ps
TIE
J
ITTE
R
H
IS
TOGR
A
M
(
H
it
s
)
Figure 52. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Internal
Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4,
External 100 Far Termination Only
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
To change the output data format to twos complement, see the
Memory Map section.
Table 8. Digital Output Coding
Code
(VIN + x) (VIN x),
Input Span = 2 V p-p (V)
Digital Output Offset Binary
(D7 ... D0)
255
+1.00
1111 1111
128
0.00
1000 0000
127
0.007813
0111 1111
0
1.00
0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 8 bits
times the sample clock rate, with a maximum of 800 Mbps
(8 bits × 100 MSPS = 800 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
a specific application, the PLL can be set up via the SPI to allow
encode rates as low as 5 MSPS. See the Memory Map section for
details on enabling this feature.
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