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| 型號： | AD9411BSVZ-170 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 170MSPS 100TQFP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 170M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.42W |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極 |
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Data Sheet
AD9411
Rev. B | Page 19 of 28
04530-0-042
S5 = AVDD
VIN+
2.8V
768mV
2.8V
VIN– = 2.8V
Figure 41. Single-Ended Analog Input Range
04530-A
-014
ANALOG INPUT COMMON MODE (V)
3.2
2.0
2.2
2.4
2.6
2.8
3.0
dB
61
60
59
58
57
56
SINAD
Figure 42. SINAD Sensitivity to Analog Input Common-Mode Voltage,
(Ain = .5 dBfs Differential Drive, S5 = 0)
LVDS OUTPUTS
The off-chip drivers provide LVDS compatible output levels. A
3.74 kΩ RSET resistor placed at Pin 7 (LVDSBIAS) to ground
sets the LVDS output current. The RSET resistor current is
ratioed on-chip, setting the output current at each output equal
to a nominal 3.5 mA (11 × IRSET). A 100 Ω differential termi-
nation resistor placed at the LVDS receiver inputs results in a
nominal 350 mV swing at the receiver. LVDS mode facilitates
interfacing with LVDS receivers in custom ASICs and FPGAs
that have LVDS capability for superior switching performance
in noisy environments. Single point-to-point network topologies
are recommended with a 100 Ω termination resistor as close to
the receiver as possible. It is recommended to keep the trace
lengths < 4 inches and to keep differential output trace lengths
as equal as possible.
CLOCK OUTPUTS (DCO+, DCO–)
The input clock is buffered on-chip and available off-chip at
DCO+ and DCO–. These clocks can facilitate latching off-chip,
providing a low skew clocking solution (see Figure 2). The on-
chip clock buffers should not drive more than 5 pF of capacitance
to limit switching transient effects on performance. The output
clocks are LVDS signals requiring 100 Ω differential termination
at receiver.
VOLTAGE REFERENCE
A stable and accurate 1.23 V voltage reference is built into the
AD9411 (VREF). The analog input full-scale range is linearly
proportional to the voltage at VREF. Note that an external
reference can be used by connecting the SENSE pin to VDD
(disabling internal reference) and driving VREF with the
external reference source. No appreciable degradation in
performance occurs when VREF is adjusted ±5%. A 0.1 μF
capacitor to ground is recommended at the VREF pin in
internal and external reference applications. Float the SENSE
pin for internal reference operation.
04530-0-043
VREF
K
A1
DISABLE
A1
SENSE
VDD
200
1V
3.3V
EXTERNAL 1.23V
REFERENCE
0.1
F
FULL
SCALE
S5 = 0
K = 1.24
S5 = 1
K = 0.62
1k
Figure 43. Using an External Reference
NOISE POWER RATIO TESTING (NPR)
NPR is a test that is commonly used to characterize the return
path of cable systems where the signals are typically QAM sig-
nals with a “noise-like” frequency spectrum. NPR performance
of the AD9411 was characterized in the lab yielding an effective
NPR = 51.2 dB at an analog input of 18 MHz. This agrees with a
theoretical maximum NPR of 51.6 dB for a 10-bit ADC at 13 dB
backoff. The rms noise power of the signal inside the notch is
compared with the rms noise level outside the notch using an
FFT. This test requires sufficiently long record lengths to
guarantee a large number of samples inside the notch. A high-
order band-stop filter that provides the required notch depth
for testing is also needed.
OBSOLETE
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