AVDD = 3.3 V, DRVDD = 3.3 V, TMIN
參數(shù)資料
型號(hào): AD9411BSVZ-170
廠商: Analog Devices Inc
文件頁(yè)數(shù): 25/28頁(yè)
文件大?。?/td> 0K
描述: IC ADC 10BIT 170MSPS 100TQFP
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝: 1
位數(shù): 10
采樣率(每秒): 170M
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.42W
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 100-TQFP-EP(14x14)
包裝: 托盤
輸入數(shù)目和類型: 1 個(gè)差分,單極
AD9411
Data Sheet
Rev. B | Page 6 of 28
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 4.
AD9411-170
AD9411-200
Parameter (Conditions)
Temp
Test
Level
Min
Typ
Max
Min
Typ
Max
Unit
Maximum Conversion Rate1
Full
VI
170
200
MSPS
Minimum Conversion Rate1
Full
V
40
MSPS
CLK+ Pulse Width High (tEH)1
Full
IV
2
12.5
2
12.5
ns
CLK+ Pulse Width Low (tEL)1
Full
IV
2
12.5
2
12.5
ns
OUTPUT (LVDS Mode)
Valid Time (tV)
Full
VI
2.0
ns
Propagation Delay (tPD)
Full
VI
3.2
4.3
3.2
4.3
ns
Rise Time (tR) (20% to 80%)
25°C
V
0.5
ns
Fall Time (tF) (20% to 80%)
25°C
V
0.5
ns
DCO Propagation Delay (tCPD)
Full
VI
1.8
2.7
3.8
1.8
2.7
3.8
ns
Data to DCO Skew (tPD–tCPD)
Full
IV
0.2
0.5
0.8
0.2
0.5
0.8
ns
Latency
Full
IV
14
Cycles
Aperture Delay (tA)
25°C
V
1.2
ns
Aperture Uncertainty (Jitter, tJ)
25°C
V
0.25
ps
rms
Out-of-Range Recovery Time
25°C
V
1
Cycles
1 All ac specifications tested by driving CLK+ and CLK– differentially.
EXPLANATION OF TEST LEVELS
I. 100% production tested.
II. 100% production tested at 25°C and sample tested at specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization testing.
V. Parameter is a typical value only.
VI.
100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100%
production tested at temperature extremes for military devices.
CLK+
AIN
tEH
tEL
tPD
tCPD
1/fS
DCO+
DCO–
N–1
N–14
N–13
N
14 CYCLES
N+1
N
CLK–
DATA OUT
04530-0-002
Figure 2. LVDS Timing Diagram
OBSOLETE
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