參數(shù)資料
型號： AD9445BSVZ-125
廠商： Analog Devices Inc
文件頁數(shù)： 40/40頁
文件大?。?/td> 0K
描述： IC ADC 14BIT 125MSPS 100-TQFP
設(shè)計(jì)資源： Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002)
Using AD8352 as an Ultralow Distortion Differential RF/IF Front End for High Speed ADCs (CN0046)
Using ADL5562 Differential Amplifier to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0110)
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 125M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 2.6W
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
輸入數(shù)目和類型： 1 個差分，單極
AD9445
Rev. 0 | Page 9 of 40
TERMINOLOGY
Analog Bandwidth (Full Power Bandwidth)
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay (tA)
Offset Error
The major carry transition should occur for an analog value of
LSB below VIN+ = VIN. Offset error is defined as the
deviation of the actual transition from that point.
The delay between the 50% point of the rising edge of the clock
and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter, tJ)
Out-of-Range Recovery Time
The sample-to-sample variation in aperture delay.
The time it takes for the ADC to reacquire the analog input
after a transition from 10% above positive full scale to 10%
above negative full scale, or from 10% below negative full scale
to 10% below positive full scale.
Clock Pulse Width and Duty Cycle
Pulse width high is the minimum amount of time that the
clock pulse should be left in the Logic 1 state to achieve rated
performance. Pulse width low is the minimum time the clock
pulse should be left in the low state. At a given clock rate, these
specifications define an acceptable clock duty cycle.
Output Propagation Delay (tPD)
The delay between the clock rising edge and the time when all
bits are within valid logic levels.
Differential Nonlinearity (DNL, No Missing Codes)
Power-Supply Rejection Ratio
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 14-bit resolution indicates that all 16,384
codes must be present over all operating ranges.
The change in full scale from the value with the supply at the
minimum limit to the value with the supply at the maximum
limit.
Signal-to-Noise and Distortion (SINAD)
Effective Number of Bits (ENOB)
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc.
The effective number of bits for a sine wave input at a given
input frequency can be calculated directly from its measured
SINAD using the following formula:
()
6.02
1.76
= SINAD
ENOB
Signal-to-Noise Ratio (SNR)
The ratio of the rms input signal amplitude to the rms value of
the sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc.
Gain Error
The first code transition should occur at an analog value of
LSB above negative full scale. The last transition should occur
at an analog value of 1 LSB below the positive full scale. Gain
error is the deviation of the actual difference between first and
last code transitions and the ideal difference between first and
last code transitions.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component
may be a harmonic. SFDR can be reported in dBc (that is, degrades
as signal level is lowered) or dBFS (always related back to converter
full scale).
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
negative full scale through positive full scale. The point used as
negative full scale occurs LSB before the first code transition.
Positive full scale is defined as a level 1 LSB beyond the last
code transition. The deviation is measured from the middle of
each particular code to the true straight line.
Temperature Drift
The temperature drift for offset error and gain error specifies
the maximum change from the initial (25°C) value to the value
at TMIN or TMAX.
Total Harmonic Distortion (THD)
The ratio of the rms input signal amplitude to the rms value of
the sum of the first six harmonic components.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product.
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