參數(shù)資料
型號(hào)： AD9445BSVZ-125
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 23/40頁(yè)
文件大?。?/td> 0K
描述： IC ADC 14BIT 125MSPS 100-TQFP
設(shè)計(jì)資源： Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002)
Using AD8352 as an Ultralow Distortion Differential RF/IF Front End for High Speed ADCs (CN0046)
Using ADL5562 Differential Amplifier to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0110)
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 14
采樣率（每秒）： 125M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 2.6W
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 托盤
輸入數(shù)目和類型： 1 個(gè)差分，單極
AD9445
Rev. 0 | Page 3 of 40
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 3.3 V, AVDD2 = 5.0 V, DRVDD = 3.3 V, LVDS mode, specified minimum sampling rate, 2.0 V p-p differential input, internal
trimmed reference (1.0 V mode), AIN = 1.0 dBFS, DCS on, unless otherwise noted. RF ENABLE = AGND.
Table 1.
AD9445BSVZ-105
AD9445BSVZ-125
Parameter
Temp
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
Full
14
Bits
ACCURACY
No Missing Codes
Full
Guaranteed
Offset Error
Full
7
+7
7
+7
mV
25°C
±3
mV
Gain Error
Full
3
+3
3
+3
% FSR
25°C
2
+2
2
+2
% FSR
Differential Nonlinearity (DNL)1
Full
0.6
±0.25
+0.65
0.6
±0.25
+0.65
LSB
5
Integral Nonlinearity (INL)1
25°C
±0.65
±0.8
LSB
Full
1.6
+1.6
2
+2
LSB
VOLTAGE REFERENCE
Output Voltage VREF = 1.0 V
Full
0.9
1.0
1.1
0.9
1.0
1.1
V
Load Regulation @ 1.0 mA
Full
±2
mV
Reference Input Current (External VREF = 1.6 V)
Full
μA
INPUT REFERRED NOISE
25°C
1.0
LSB rms
ANALOG INPUT
Input Span
VREF = 1.6 V
Full
3.2
V p-p
VREF = 1.0 V
Full
2.0
V p-p
Internal Input Common-Mode Voltage
Full
3.5
V
External Input Common-Mode Voltage
Full
3.1
3.9
3.1
3.9
V
Input Resistance2
Full
1
kΩ
Input Capacitance2
Full
6
pF
POWER SUPPLIES
Supply Voltage
AVDD1
Full
3.14
3.3
3.46
3.14
3.3
3.46
V
AVDD2
Full
4.75
5.0
5.25
4.75
5.0
5.25
V
DRVDD—LVDS Outputs
Full
3.0
3.6
3.0
3.6
V
DRVDD—CMOS Outputs
Full
3.0
3.3
3.6
3.0
3.3
3.6
V
Supply Current1
AVDD1
Full
335
364
384
424
mA
Full
169
196
172
199
mA
IDRVDD1—LVDS Outputs
Full
63
78
63
78
mA
IDRVDD1—CMOS Outputs
Full
14
mA
PSRR
Offset
Full
1
mV/V
Gain
Full
0.2
%/V
POWER CONSUMPTION
LVDS Outputs
Full
2.2
2.4
2.3
2.6
W
CMOS Outputs (DC Input)
Full
2.0
2.1
W
1 Measured at the maximum clock rate, fIN = 15 MHz, full-scale sine wave, with a 100 Ω differential termination on each pair of output bits for LVDS output mode and
approximately 5 pF loading on each output bit for CMOS output mode.
2 Input capacitance or resistance refers to the effective impedance between one differential input pin and AGND. Refer to Figure 6 for the equivalent analog input structure.
3 For RF ENABLE = AVDD1, IAVDD2 increases by ~30 mA, which increases power dissipation.
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