參數(shù)資料
型號(hào)： AD9512BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 26/48頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK DIST 5OUT PLL 48LFCSP
標(biāo)準(zhǔn)包裝： 750
類(lèi)型： 扇出緩沖器（分配），除法器
PLL： 無(wú)
輸入： 時(shí)鐘
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:5
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.2GHz
除法器/乘法器： 是/無(wú)
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
AD9512
Rev. A | Page 32 of 48
SINGLE-CHIP SYNCHRONIZATION
SYNCB—Hardware SYNC
The AD9512 clocks can be synchronized to each other at any
time. The outputs of the clocks are forced into a known state
with respect to each other and then allowed to continue
clocking from that state in synchronicity. Before a
synchronization is done, the FUNCTION Pin must be set as the
input (58h<6:5> = 01b). Synchronization is done by forcing the
FUNCTION pin low, creating a SYNCB signal and then
releasing it.
See the SYNCB: 58h<6:5> = 01b section for a more detailed
description of what happens when the SYNCB: 58h<6:5> = 01b
signal is issued.
Soft SYNC—Register 58h<2>
A soft SYNC can be issued by means of a bit in
Register 58h<2>. This soft SYNC works the same as the
SYNCB, except that the polarity is reversed. A 1 written to this
bit forces the clock outputs into a known state with respect to
each other. When a 0 is subsequently written to this bit, the
clock outputs continue clocking from that state in
synchronicity.
MULTICHIP SYNCHRONIZATION
The AD9512 provides a means of synchronizing two or more
AD9512s. This is not an active synchronization; it requires user
monitoring and action. The arrangement of two AD9512s to be
synchronized is shown in Figure 29.
Synchronization of two or more AD9512s requires a fast clock
and a slow clock. The fast clock can be up to 1 GHz and can be
the clock driving the master AD9512 CLK1 input or one of the
outputs of the master. The fast clock acts as the input to the
distribution section of the slave AD9512 and is connected to its
CLK1 input.
The slow clock is the clock that is synchronized across the two
chips. This clock must be no faster than one-fourth of the fast
clock, and no greater than 250 MHz. The slow clock is taken
from one of the outputs of the master AD9512 and acts as a
DSYNC input to the slave AD9512. One of the outputs of the
slave must provide this same frequency back to the DSYNCB
input of the slave.
Multichip synchronization is enabled by writing to
Register 58h<0> = 1b on the slave AD9512. When this bit
is set, the STATUS pin becomes the output for the SYNC
signal. A low signal indicates an in-sync condition, and
a high indicates an out-of-sync condition.
Register 58h<1> selects the number of fast clock cycles that are
the maximum separation of the slow clock edges that are
considered synchronized. When 58h<1> = 0b (default), the
slow clock edges must be coincident within 1 to 1.5 high speed
clock cycles. If the coincidence of the slow clock edges is closer
than this amount, the SYNC flag stays low. If the coincidence of
the slow clock edges is greater than this amount, the SYNC flag
is set high. When Register 58h<1> = 1b, the amount of
coincidence required is 0.5 fast clock cycles to 1 fast clock
cycles.
Whenever the SYNC flag is set (high), indicating an out-of-sync
condition, a SYNCB signal applied simultaneously at the
FUNCTION pins of both AD9512s brings the slow clocks into
synchronization.
05287-
093
AD9512
MASTER
FAST CLOCK
<1GHz
SLOW CLOCK
<250MHz
AD9512
SLAVE
FAST CLOCK
<1GHz
SLOW
CLOCK
<250MHz
SYNC
DETECT
DSYNC
DSYNCB
OUTY
OUTM
OUTN
FSYNC
SYNCSTATUS
FUNCTION
(SYNCB)
FUNCTION
(SYNCB)
SYNCB
CLK1
Figure 29. Multichip Synchronization
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