參數(shù)資料
型號(hào): AD9516-2BCPZ-REEL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 62/80頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK PLL/VCO 2.2GHZ 64LFCSP
標(biāo)準(zhǔn)包裝: 750
類型: 時(shí)鐘發(fā)生器,扇出配送
PLL:
輸入: 時(shí)鐘
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:14
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.33GHz
除法器/乘法器: 是/無(wú)
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 帶卷 (TR)
配用: AD9516-2/PCBZ-ND - BOARD EVAL FOR AD9516-2 2.2GHZ
Data Sheet
AD9516-2
Rev. C | Page 65 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
0x01D
4
PLL status
Disables the PLL status register readback.
register disable
0: PLL status register enable (default).
1: PLL status register disable.
3
LD pin comparator
enable
Enables the LD pin voltage comparator. This function is used with the LD pin current source lock detect mode. When
in the internal (automatic) holdover mode, this function enables the use of the voltage on the LD pin to determine if
the PLL was previously in a locked state (see Figure 53). Otherwise, this function can be used with the REFMON and
STATUS pins to monitor the voltage on this pin.
0: disables LD pin comparator; internal/automatic holdover controller treats this pin as true (high) (default).
1: enables LD pin comparator.
2
Holdover enable
Along with Bit 0, enables the holdover function. Automatic holdover must be disabled during VCO calibration.
0: holdover disabled (default).
1: holdover enabled.
1
External
Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.)
holdover control
0: automatic holdover mode—holdover controlled by automatic holdover circuit. (default)
1: external holdover mode—holdover controlled by SYNC pin.
0
Holdover enable
Along with Bit 2, enables the holdover function. Automatic holdover must be disabled during VCO calibration.
0: holdover disabled (default).
1: holdover enabled.
0x01F
6
VCO cal finished
Read-only register. Indicates status of the VCO calibration.
0: VCO calibration not finished.
1: VCO calibration finished.
5
Holdover active
Read-only register. Indicates if the part is in the holdover state (see Figure 53). This is not the same as holdover enabled.
0: not in holdover.
1: holdover state active.
4
REF2 selected
Read-only register. Indicates which PLL reference is selected as the input to the PLL.
0: REF1 selected (or differential reference if in differential mode).
1: REF2 selected.
3
VCO frequency >
threshold
Read-only register. Indicates if the VCO frequency is greater than the threshold (see Table 16, REF1, REF2, and VCO
frequency status monitor).
0: VCO frequency is less than the threshold.
1: VCO frequency is greater than the threshold.
2
REF2 frequency >
threshold
Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by
Register 0x01A, Bit 6.
0: REF2 frequency is less than threshold frequency.
1: REF2 frequency is greater than threshold frequency.
1
REF1 frequency >
threshold
Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by Register 0x01A, Bit 6.
0: REF1 frequency is less than threshold frequency.
1: REF1 frequency is greater than threshold frequency.
0
Digital lock detect
Read-only register. Digital lock detect.
0: PLL is not locked.
1: PLL is locked.
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