- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9088 > AD9516-2BCPZ-REEL7 (Analog Devices Inc)IC CLOCK PLL/VCO 2.2GHZ 64LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9516-2BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 76/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK PLL/VCO 2.2GHZ 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:14 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.33GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9516-2/PCBZ-ND - BOARD EVAL FOR AD9516-2 2.2GHZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁當(dāng)前第76頁第77頁第78頁第79頁第80頁
AD9516-2
Data Sheet
Rev. C | Page 78 of 80
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9516 provide the lowest jitter
clock signals that are available from the AD9516. The LVPECL
outputs (because they are open emitter) require a dc termination
to bias the output transistors. The simplified equivalent circuit
in Figure 59 shows the LVPECL output stage.
In most applications, an LVPECL far-end Thevenin termination
(see Figure 71) or Y-termination (see Figure 72) is recommended.
In each case, the VS of the receiving buffer should match the
VS_LVPECL. If it does not, ac coupling is recommended (see
The resistor network is designed to match the transmission line
impedance (50 ) and the switching threshold (VS 1.3 V).
VS_LVPECL
LVPECL
50
SINGLE-ENDED
(NOT COUPLED)
VS
VS_DRV
LVPECL
127
83
06421-
145
Figure 71. DC-Coupled 3.3 V LVPECL, Far-End Thevenin Termination
VS_LVPECL
LVPECL
Z0 = 50
VS = 3.3V
LVPECL
50
Z0 = 50
06421-
147
Figure 72. DC-Coupled 3.3 V LVPECL, Y-Termination
VS_LVPECL
LVPECL
100 DIFFERENTIAL
(COUPLED)
TRANSMISSION LINE
VS
LVPECL
100
0.1nF
200
06421-
146
Figure 73. AC-Coupled LVPECL with Parallel Transmission Line
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the
case shown in Figure 72, where VS_LVPECL = 2.5 V, the 50
termination resistor that is connected to ground should be
changed to 19 .
Thevenin-equivalent termination uses a resistor network to provide
50 termination to a dc voltage that is below VOL of the LVPECL
driver. In this case, VS_LVPECL on the AD9516 should equal VS
of the receiving buffer. Although the resistor combination shown
in Figure 72 results in a dc bias point of VS_LVPECL 2 V, the
actual common-mode voltage is VS_LVPECL 1.3 V because
additional current flows from the AD9516 LVPECL driver through
the pull-down resistor.
The circuit is identical when VS_LVPECL = 2.5 V, except that
the pull-down resistor is 62.5 and the pull-up resistor is 250 .
LVDS CLOCK DISTRIBUTION
The AD9516 provides four clock outputs (OUT6 to OUT9) that
are selectable as either CMOS or LVDS level outputs. LVDS is a
differential output option that uses a current mode output stage.
The nominal current is 3.5 mA, which yields 350 mV output swing
across a 100 resistor. An output current of 7 mA is also available
in cases where a larger output swing is required. The LVDS
output meets or exceeds all ANSI/TIA/EIA-644 specifications.
A recommended termination circuit for the LVDS outputs is
shown in Figure 74.
VS
LVDS
100
DIFFERENTIAL (COUPLED)
VS
LVDS
100
06421-
047
Figure 74. LVDS Output Termination
See the AN-586 Application Note, LVDS Data Outputs for High-
Speed Analog-to-Digital Converters for more information on LVDS.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| X9418YV24I-2.7 | IC XDCP DUAL 64-TAP 2.5K 24TSSOP |
| X9418YV24I | IC XDCP DUAL 64-TAP 2.5K 24TSSOP |
| X9418YV24-2.7 | IC XDCP DUAL 64-TAP 2.5K 24TSSOP |
| X9420WS16IT1 | IC XDCP SGL 64-TAP 10K 16-SOIC |
| X9410WV24-2.7T1 | IC XDCP DUAL 64-TAP 10K 24-TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9516-3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Output Clock Generator with Integrated 2.0 GHz VCO |
| AD9516-3/PCBZ | 功能描述:BOARD EVAL FOR AD9516-3 2.0GHZ RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9516-3BCPZ | 功能描述:IC CLOCK PLL/VCO 2GHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| AD9516-3BCPZ-REEL7 | 功能描述:IC CLOCK PLL/VCO 2GHZ 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無 頻率 - 最大:240MHz 除法器/乘法器:是/無 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR) |
| AD9516-4 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Output Clock Generator with Integrated 1.6 GHz VCO |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。