參數(shù)資料
型號(hào): AD9517-1A/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 4/80頁
文件大小: 0K
描述: BOARD EVALUATION FOR AD9517-1A
設(shè)計(jì)資源: AD9517 Eval Brd Schematics
AD9517 Gerber Files
AD9517-1 BOM
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9517-1A
主要屬性: 2 輸入,12 輸出,2.5GHz VCO
次要屬性: CMOS,LVPECL 和 LVDS 兼容
已供物品:
AD9517-1
Data Sheet
Rev. E | Page 12 of 80
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1
40
fs rms
BW = 12 kHz to 20 MHz
CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4
80
fs rms
BW = 12 kHz to 20 MHz
CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16
215
fs rms
Calculated from SNR of ADC method;
DCC not used for even divides
CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5
245
fs rms
Calculated from SNR of ADC method; DCC on
LVDS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2;
VCO Divider Not Used
85
fs rms
BW = 12 kHz to 20 MHz
CLK = 1 GHz; LVDS = 200 MHz; Divider = 5
113
fs rms
BW = 12 kHz to 20 MHz
CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16
280
fs rms
Calculated from SNR of ADC method;
DCC not used for even divides
CMOS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16
365
fs rms
Calculated from SNR of ADC method;
DCC not used for even divides
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
210
fs rms
Calculated from SNR of ADC method
LVDS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
285
fs rms
Calculated from SNR of ADC method
CMOS OUTPUT ADDITIVE TIME JITTER
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
350
fs rms
Calculated from SNR of ADC method
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