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| 型號： | AD9517-1A/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 46/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9517-1A |
| 設(shè)計資源： | AD9517 Eval Brd Schematics AD9517 Gerber Files AD9517-1 BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計時，時鐘發(fā)生器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9517-1A |
| 主要屬性： | 2 輸入，12 輸出，2.5GHz VCO |
| 次要屬性： | CMOS，LVPECL 和 LVDS 兼容 |
| 已供物品： | 板 |
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AD9517-1
Data Sheet
Rev. E | Page 50 of 80
POWER-DOWN MODES
Chip Power-Down via PD
The AD9517 can be put into a power-down condition by
pulling the PD pin low. Power-down turns off most of the
functions and currents inside the AD9517. The chip remains
in this power-down state until PD is brought back to logic high.
When the AD9517 wakes up, it returns to the settings
programmed into its registers prior to the power-down, unless
the registers are changed by new programming while the PD
pin is held low.
The PD power-down shuts down the currents on the chip, except
the bias current that is necessary to maintain the LVPECL outputs
in a safe shutdown mode. This is needed to protect the LVPECL
output circuitry from damage that could be caused by certain
termination and load configurations when tristated. Because
this is not a complete power-down, it can be called sleep mode.
When the AD9517 is in a PD power-down, the chip is in the
following state:
The PLL is off (asynchronous power-down).
The VCO is off.
The CLK input buffer is off.
All dividers are off.
All LVDS/CMOS outputs are off.
All LVPECL outputs are in safe off mode.
The serial control port is active, and the chip responds to
commands.
If the AD9517 clock outputs must be synchronized to each
other, a SYNC is required upon exiting power-down (see the
Synchronizing the Outputs—Sync Function section). A VCO
calibration is not required when exiting power-down.
PLL Power-Down
The PLL section of the AD9517 can be selectively powered down.
There are three PLL operating modes set by Register 0x010[1:0],
as shown in Table 54.
In asynchronous power-down mode, the device powers down as
soon as the registers are updated.
In synchronous power-down mode, the PLL power-down is
gated by the charge pump to prevent unwanted frequency jumps.
The device goes into power-down on the occurrence of the next
charge pump event after the registers are updated.
Distribution Power-Down
The distribution section can be powered down by writing
Register 0x230[1] = 1b. This turns off the bias to the distribution
section. If the LVPECL power-down mode is normal operation
(00b), it is possible for a low impedance load on that LVPECL
output to draw significant current during this power-down. If
the LVPECL power-down mode is set to 11b, the LVPECL
output is not protected from reverse bias and may be damaged
under certain termination conditions.
Individual Clock Output Power-Down
Any of the clock distribution outputs can be powered down
individually by writing to the appropriate registers. The register
map details the individual power-down settings for each output
(see Table 52). The LVDS/CMOS outputs can be powered down,
regardless of their output load configuration.
The LVPECL outputs have multiple power-down modes
(see Table 56), which give some flexibility in dealing with the
various output termination conditions. When the mode is set to
10b, the LVPECL output is protected from reverse bias to
2 VBE + 1 V. If the mode is set to 11b, the LVPECL output is
not protected from reverse bias and can be damaged under
certain termination conditions. This setting also affects the
operation when the distribution block is powered down with
Register 0x230[1] = 1b (see the Distribution Power-Down
section).
Individual Circuit Block Power-Down
Other AD9517 circuit blocks (such as CLK, REF1, and REF2)
can be powered down individually. This gives flexibility in
configuring the part for power savings whenever certain chip
functions are not needed.
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