參數資料
型號: AD9517-4ABCPZ-RL7
廠商: Analog Devices Inc
文件頁數: 14/80頁
文件大?。?/td> 0K
描述: IC CLOCK GEN 1.8GHZ VCO 48LFCSP
設計資源: High Performance, Dual Channel IF Sampling Receiver (CN0140)
標準包裝: 750
類型: 時鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS,LVPECL
電路數: 1
比率 - 輸入:輸出: 1:12
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.8GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應商設備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
Data Sheet
AD9517-4
Rev. E | Page 21 of 80
–140
–145
–150
–155
–160
–165
–170
0.1
1
100
10
P
F
D
P
HAS
E
NO
IS
E
RE
F
E
RRE
D
T
O
P
F
D
I
NP
UT
(d
Bc/
Hz
)
PFD FREQUENCY (MHz)
06428-
013
Figure 13. PFD Phase Noise Referred to PFD Input vs. PFD Frequency
–210
–224
–222
–220
–218
–216
–214
–212
0
2.5
2.0
1.5
1.0
0.5
P
LL
FIGU
R
E
OF
M
E
R
IT
(
dB
c
/H
z
)
SLEW RATE (V/ns)
06428-
136
Figure 14. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/REFIN
2.1
0.9
1.1
1.3
1.5
1.7
1.9
1.45
1.55
1.65
1.75
1.50
1.60
1.70
1.80
V
C
O
TU
N
IN
G
V
OLTA
GE
(
V
)
FREQUENCY (GHz)
06428-
201
Figure 15. VCO Tuning Voltage vs. Frequency
(Note that VCO calibration centers the dc tuning voltage
for the PLL setup that is active during calibration.)
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
10
0
CENTER 122.88MHz
SPAN 50MHz
5MHz/DIV
R
EL
A
T
IVE
PO
W
ER
(d
B
)
06428-
202
Figure 16. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz;
LBW = 135 kHz; ICP = 3 mA; fVCO = 1.475 GHz
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
10
0
CENTER 122.88MHz
SPAN 1MHz
100kHz/DIV
R
EL
A
T
IVE
PO
W
ER
(d
B
)
06428-
203
Figure 17. Output Spectrum, LVPECL; 122.88 MHz; PFD = 15.36 MHz;
LBW = 135 kHz; ICP = 3 mA; fVCO = 1.475 GHz
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
10
0
CENTER 122.88MHz
SPAN 1MHz
100kHz/DIV
R
EL
A
T
IVE
PO
W
ER
(d
B
)
06428-
204
Figure 18. Output Spectrum, LVDS; 122.88 MHz; PFD = 15.36 MHz;
LBW = 135 kHz; ICP = 3 mA; fVCO = 1.475 GHz
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