參數(shù)資料
型號(hào): AD9517-4ABCPZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 63/80頁
文件大?。?/td> 0K
描述: IC CLOCK GEN 1.8GHZ VCO 48LFCSP
設(shè)計(jì)資源: High Performance, Dual Channel IF Sampling Receiver (CN0140)
標(biāo)準(zhǔn)包裝: 750
類型: 時(shí)鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:12
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.8GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
AD9517-4
Data Sheet
Rev. E | Page 66 of 80
Table 55. Fine Delay Adjust—OUT4 to OUT7
Reg.
Addr.
(Hex)
Bits
Name
Description
0x0A0
0
OUT4 delay bypass
Bypasses or uses the delay function.
0: uses delay function.
1: bypasses delay function (default).
0x0A1
[5:3]
OUT4 ramp capacitors
Selects the number of ramp capacitors used by the delay function. The combination of the
number of the capacitors and the ramp current sets the delay full scale.
5
4
3
Number of Capacitors
0
4 (default)
0
1
3
0
1
0
3
0
1
2
1
0
3
1
0
1
2
1
0
2
1
[2:0]
OUT4 ramp current
Ramp current for the delay function. The combination of the number of capacitors and the ramp
current sets the delay full scale.
2
1
0
Current (A)
0
200 (default)
0
1
400
0
1
0
600
0
1
800
1
0
1000
1
0
1
1200
1
0
1400
1
1600
0x0A2
[5:0]
OUT4 delay fraction
Selects the fraction of the full-scale delay desired (6-bit binary).
A setting of 000000b gives zero delay.
Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).
0x0A3
0
OUT5 delay bypass
Bypasses or uses the delay function.
0: uses delay function.
1: bypasses delay function (default).
0x0A4
[5:3]
OUT5 ramp capacitors
Selects the number of ramp capacitors used by the delay function. The combination of the
number of the capacitors and the ramp current sets the delay full scale.
5
4
3
Number of Capacitors
0
4 (default)
0
1
3
0
1
0
3
0
1
2
1
0
3
1
0
1
2
1
0
2
1
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