參數(shù)資料
型號: AD9518-3ABCPZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 2/64頁
文件大?。?/td> 0K
描述: IC CLOCK GEN 6CH 2GHZ 48LFCSP
標(biāo)準(zhǔn)包裝: 750
類型: 時鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:6
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.25GHz
除法器/乘法器: 是/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
AD9518-3
Data Sheet
Rev. B | Page 10 of 64
SERIAL CONTROL PORT
Table 13.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CS (INPUT)
CS has an internal 30 kΩ pull-up resistor
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
3
μA
Input Logic 0 Current
110
μA
Input Capacitance
2
pF
SCLK (INPUT)
SCLK has an internal 30 kΩ pull-down resistor
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
110
μA
Input Logic 0 Current
1
μA
Input Capacitance
2
pF
SDIO (WHEN INPUT)
Input Logic 1 Voltage
2.0
V
Input Logic 0 Voltage
0.8
V
Input Logic 1 Current
10
nA
Input Logic 0 Current
20
nA
Input Capacitance
2
pF
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
2.7
V
Output Logic 0 Voltage
0.4
V
TIMING
Clock Rate (SCLK, 1/tSCLK)
25
MHz
Pulse Width High, tHIGH
16
ns
Pulse Width Low, tLOW
16
ns
SDIO to SCLK Setup, tDS
2
ns
SCLK to SDIO Hold, tDH
1.1
ns
SCLK to Valid SDIO and SDO, tDV
8
ns
CS to SCLK Setup and Hold, tS, tH
2
ns
CS Minimum Pulse Width High, tPWH
3
ns
PD, SYNC, AND RESET PINS
Table 14.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT CHARACTERISTICS
These pins each have a 30 kΩ internal pull-up
resistor
Logic 1 Voltage
2.0
V
Logic 0 Voltage
0.8
V
Logic 1 Current
1
μA
Logic 0 Current
110
μA
Capacitance
2
pF
RESET TIMING
Pulse Width Low
50
ns
SYNC TIMING
Pulse Width Low
1.5
High speed
clock cycles
High speed clock is CLK input signal
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