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參數資料
| 型號： | AD9518-3ABCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 54/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN 6CH 2GHZ 48LFCSP |
| 標準包裝： | 750 |
| 類型： | 時鐘發(fā)生器，扇出配送 |
| PLL： | 是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | LVPECL |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.25GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
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AD9518-3
Data Sheet
Rev. B | Page 58 of 64
Reg.
Addr
(Hex)
Bits
Name
Description
0x1E1
4
Power down clock input section
Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
0: normal operation (default).
1: power-down.
3
Power down VCO clock interface
Powers down the interface block between VCO and clock distribution.
0: normal operation (default).
1: power-down.
2
Power down VCO and CLK
Powers down both VCO and CLK input.
0; normal operation (default).
1: power-down.
1
Select VCO or CLK
Selects either the VCO or the CLK as the input to VCO divider.
0: selects external CLK as input to VCO divider (default).
1: selects VCO as input to VCO divider; cannot bypass VCO divider when this is selected.
0
Bypass VCO divider
Bypasses or uses the VCO divider.
0: uses VCO divider (default).
1: bypasses VCO divider; cannot select VCO as input when this is selected.
Table 48. System
Reg.
Addr.
(Hex)
Bits
Name
Description
0x230
2
Power down SYNC
Powers down the sync function.
0: normal operation of the sync function (default).
1: powers down sync circuitry.
1
Powers down the reference for distribution section.
Power down distribution
reference
0: normal operation of the reference for the distribution section (default).
1: powers down the reference for the distribution section.
0
Soft sync
The soft sync bit works the same as the SYNC pin, except that the polarity of the bit
is reversed. That is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a sync.
0: same as SYNC high (default).
1: same as SYNC low.
Table 49. Update All Registers
Reg.
Addr
(Hex)
Bits
Name
Description
0x232
0
Update all registers
This bit must be set to 1b to transfer the contents of the buffer registers into the active
registers, which happens on the next SCLK rising edge. This bit is self-clearing; that is,
it does not have to be set back to 0b.
1 (self-clearing): updates all active registers to the contents of the buffer registers.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9518-3A-PCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:6-Output Clock Generator with 6-Output Clock Generator with |
| AD9518-3BCPZ | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9518-3BCPZ-REEL7 | 制造商:Analog Devices 功能描述:Clock Generator 48-Pin LFCSP EP T/R |
| AD9518-4 | 制造商:AD 制造商全稱:Analog Devices 功能描述:6-Output Clock Generator with Integrated 1.6 GHz VCO |
| AD9518-4A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9518-4A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
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