參數(shù)資料
型號(hào): AD9518-3ABCPZ-RL7
廠商: Analog Devices Inc
文件頁(yè)數(shù): 47/64頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK GEN 6CH 2GHZ 48LFCSP
標(biāo)準(zhǔn)包裝: 750
類型: 時(shí)鐘發(fā)生器,扇出配送
PLL:
輸入: CMOS,LVDS,LVPECL
輸出: LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:6
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.25GHz
除法器/乘法器: 是/無(wú)
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
Data Sheet
AD9518-3
Rev. B | Page 51 of 64
Reg.
Addr.
(Hex)
Bits
Name
Description
0x01A
6
Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO
frequency monitor’s detection threshold (see Table 15: REF1, REF2, and VCO frequency status monitor).
Reference
frequency monitor
threshold
0: frequency valid if frequency is above the higher frequency threshold (default).
1: frequency valid if frequency is above the lower frequency threshold.
[5:0]
LD pin control
Selects the signal that is connected to the LD pin.
5
4
3
2
1
0
Level or
Dynamic
Signal
Signal at LD Pin
0
LVL
Digital lock detect (high = lock, low = unlock) (default).
0
1
DYN
P-channel, open-drain lock detect (analog lock detect).
0
1
0
DYN
N-channel, open-drain lock detect (analog lock detect).
0
1
HIZ
High-Z LD pin.
0
1
0
CUR
Current source lock detect (110 μA when DLD is true).
0
X
LVL
Ground (dc); for all other cases of 0XXXXXb not specified previously.
The selections that follow are the same as REFMON.
1
0
LVL
Ground (dc).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active
high.
1
0
1
0
LVL
Status of unselected reference (not available in differential mode);
active high.
1
0
1
LVL
Status REF1 frequency; active high.
1
0
1
0
LVL
Status REF2 frequency; active high.
1
0
1
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
0
1
LVL
Status of VCO frequency (active high).
1
0
1
0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
0
1
LVL
Digital lock detect (DLD); active high.
1
0
1
0
LVL
Holdover active; active high.
1
0
1
LVL
Not available. Do not use.
1
0
LVL
VS (PLL supply).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
1
0
1
0
LVL
Status of unselected reference (not available in differential mode);
active low.
1
0
1
LVL
Status of REF1 frequency; active low.
1
0
LVL
Status of REF2 frequency; active low.
1
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
LVL
Status of VCO frequency; active low.
1
0
LVL
Selected reference (low = REF2, high = REF1).
1
0
1
LVL
Digital lock detect (DLD); active low.
1
0
LVL
Holdover active; active low.
1
LVL
Not available. Do not use.
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