參數(shù)資料
型號(hào)： AD9547BCPZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 45/104頁
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告： AD9547 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 750
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
Data Sheet
AD9547
Rev. E | Page 45 of 104
At power-up, the multifunction pins can be used to force the device
into certain configurations as defined in the Initial M0 to M7 Pin
Programming section. This functionality, however, is valid only
during power-up or following a reset, after which the pins can be
reconfigured via the serial programming port or via the EEPROM.
IRQ PIN
The AD9547 has a dedicated interrupt request (IRQ) pin. The
IRQ pin output mode register (Register 0x0208, Bits[1:0]) controls
how the IRQ pin asserts an interrupt based on the value of the
two bits, as shown in Table 27.
Table 27. IRQ PinControl—Register 0x0208, Bits[1:0]
Setting
Description
00
The IRQ pinis high impedance when deasserted and
active low when asserted and requires an external
pull-up resistor (this is the default operatingmode).
01
The IRQ pinis high impedance when deasserted and
active high when asserted and requires an external
pull-down resistor.
10
The IRQ pinis Logic 0 when deasserted and Logic 1
when asserted.
11
The IRQ pinis Logic 1 when deasserted and Logic 0
when asserted.
The AD9547 asserts the IRQ pin when any of the bits in the IRQ
monitor registers (Address 0x0D02 to Address 0x0D09) are
Logic 1. Each bit in these registers is associated with an internal
function that is capable of producing an interrupt. Furthermore,
each bit of the IRQ monitor register is the result of a logical AND
of the associated internal interrupt signal and the corresponding
bit in the IRQ mask register (Address 0x0209 to Address 0x0210).
That is, the bits in the IRQ mask register have a one-to-one cor-
respondence with the bits in the IRQ monitor register. When an
internal function produces an interrupt signal and the associated
IRQ mask bit is set, the corresponding bit in the IRQ monitor
register is set.
The user should be aware that clearing a bit in the IRQ mask
register removes only the mask associated with the internal
interrupt signal. It does not clear the corresponding bit in the
IRQ monitor register.
The IRQ pin is the result of a logical OR of all the IRQ monitor
register bits. Thus, the AD9547 asserts the IRQ pin as long as any
of the IRQ monitor register bits are Logic 1. Note that it is
possible to have multiple bits set in the IRQ monitor register.
Therefore, when the AD9547 asserts the IRQ pin, it may indicate
an interrupt from several different internal functions. The IRQ
monitor register provides the user with a means to interrogate
the AD9547 to determine which internal function(s) produced
the interrupt.
Typically, when the AD9547 asserts the IRQ pin, the user inter-
rogates the IRQ monitor register to identify the source of the
interrupt request. After servicing an indicated interrupt, the user
should clear the associated IRQ monitor register bit via the IRQ
clearing registers (Address 0x0A04 to Address 0x0A0B). The bits
in the IRQ clearing register have a one-to-one correspondence
with the bits in the IRQ monitor register. Note that the IRQ
clearing register is autoclearing. The IRQ pin remains asserted
until the user clears all of the bits in the IRQ monitor register
that indicate an interrupt.
It is also possible to collectively clear all of the IRQ monitor
register bits by setting the reset all IRQs bit in the reset functions
register (Register 0x0A03, Bit 1). Note that this is an autoclearing
bit. Setting this bit results in deassertion of the IRQ pin. Alter-
natively, the user can program any of the multifunction pins to
clear all IRQs. This allows the user to clear all IRQs by means of
a hardware pin rather than by a serialI/O port operation.
Note that the IRQ function detects a state change in the function
that is being monitored. However, if IRQs are cleared (or if they
are enabled for the first time), an IRQ will not be generated for
a pre-existing condition. The state must change after the IRQ is
enabled. For example, if REFA is already invalid before a "REFA
invalid" IRQ is enabled, an IRQ will not be generated.
WATCHDOG TIMER
The watchdog timer is a general-purpose, programmable timer.
To set its timeout period, the user writes to the 16-bit watchdog
timer register (Address 0x0211 and Address 0x0212). A value of
zero in this register disables the timer. A nonzero value sets the
timeout period in units of milliseconds (ms), giving the watchdog
timer a range of 1 ms to 65,535 ms. The relative accuracy of the
timer is approximately 0.1%with an uncertainty of 0.5 ms.
If enabled, the timer runs continuously and generates a timeout
event whenever the timeout period expires. The user has access
to the watchdog timer status via the IRQ mechanism and the
multifunction pins (M0 to M7). In the case of the multifunction
pins, the timeout event of the watchdog timer is a pulse that
lasts 32 system clock periods.
There are two ways to reset the watchdog timer (thereby pre-
venting it from causing a timeout event). The first is by writing
a Logic 1 to the autoclearing reset watchdog bit in the reset
functions register (Register 0x0A03, Bit 0). Alternatively, the
user can program any of the multifunction pins to reset the
watchdog timer. This allows the user toreset the timer by means
of a hardware pin rather than bya serial I/O port operation.
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