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參數(shù)資料
型號(hào)： AD9547BCPZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 56/104頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告： AD9547 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 750
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 帶卷 (TR)
Data Sheet
AD9547
Rev. E | Page 55 of 104
IC SERIAL PORT OPERATION
The I2C interface has the advantage of requiring only two
control pins and is a de facto standard throughout the I2C
industry. However, its disadvantage is programming speed,
which is 400 kbps maximum. The AD9547 I2C port design is
based on the I2C fast mode standard from Philips, so it supports
both the 100 kHz standard mode and the 400 kHz fast mode.
Fast mode imposes a glitch tolerance requirement on the control
signals; that is, the input receivers ignore pulses of less than
50 ns duration.
The AD9547 I2C port consists of a serial data line (SDA) and
a serial clock line (SCL). In an I2C bus system, the AD9547 is
connected to the serial bus (data bus SDA and clock bus SCL)
as a slave device; that is, no clock is generated by the AD9547.
The AD9547 uses direct 16-bit memory addressing instead of
traditional 8-bit memory addressing.
The AD9547 allows for up to seven unique slave devices to occupy
the I2C bus. These are accessed via a 7-bit slave address that is
transmitted as part of an I2C packet. Only the device with a match-
ing slave address responds to subsequent I2C commands. The
device slave address is 1001xxx (the last three bits are determined
by the M0 to M2 pins). The four MSBs (1001) are hardwired,
whereas the three LSBs (xxx, determined by the M0 to M2 pins)
are programmable via the power-up state of the multifunction
I2C Bus Characteristics
A summary of the various I2C protocols appears in Table 35.
Table 35. I2C Bus Abbreviation Definitions
Abbreviation
Definition
S
Start
Sr
Repeated start
P
Stop
A
Acknowledge
A
No acknowledge
W
Write
R
Read
The transfer of data appears graphically in Figure 59. One clock
pulse is generated for each data bit transferred. The data on the
SDA line must be stable during the high period of the clock.
The high or low state of the data line can change only when the
clock signal on the SCL line is low.
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
SDA
SCL
08300-
035
Figure 59. Valid Bit Transfer
Start/stop functionality appears graphically in Figure 60. The
start condition is characterized by a high-to-low transition on
the SDA line while SCL is high. The start condition is always
generated by the master to initialize data transfer. The stop
condition is characterized by a low-to-high transition on the
SDA line while SCL is high. The stop condition is always
generated by the master to terminate data transfer.
SDA
START CONDITION
STOP CONDITION
SCL
SP
08300-
036
Figure 60. Start and Stop Condition
Every byte on the SDA line must be eight bits long. Each byte
must be followed by an acknowledge bit. Bytes are sent MSB first.
The acknowledge bit (A) is the ninth bit attached to any 8-bit
data byte. An acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has been received. It is done by pulling the SDA line low
during the ninth clock pulse after each 8-bit data byte.
The no acknowledge bit (A) is the ninth bit attached to any 8-bit
data byte. A no acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has not been received. It is done by leaving the SDA line
high during the ninth clock pulse after each 8-bit data byte.
12
89
12
3 TO 7
89
10
SDA
SCL
S
MSB
ACK FROM
SLAVE RECEIVER
ACK FROM
SLAVE RECEIVER
P
08
30
0-
03
7
Figure 61. Acknowledge Bit
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