參數(shù)資料
型號(hào): AD9551BCPZ-REEL7
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 32/40頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK GEN TRANSLATOR 40LFCSP
標(biāo)準(zhǔn)包裝: 1
類(lèi)型: 時(shí)鐘發(fā)生器
PLL:
輸入: 晶體
輸出: CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 900MHz
除法器/乘法器: 無(wú)/無(wú)
電源電壓: 3.3V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 40-VFQFN 裸露焊盤(pán),CSP
供應(yīng)商設(shè)備封裝: 40-LFCSP-VQ(6x6)
包裝: 標(biāo)準(zhǔn)包裝
其它名稱(chēng): AD9551BCPZ-REEL7DKR
AD9551
Rev. B | Page 38 of 40
OUT1 Driver Control (Register 0x32)
Table 33.
Address
Bit
Bit Name
Description
0x32
7
OUT1 drive strength
Controls the output drive capability of the OUT1 driver.
0 = weak.
1 = strong (default).
6
OUT1 power-down
Controls power-down functionality of the OUT1 driver.
0 = OUT1 active (default).
1 = OUT1 powered down.
[5:3]
OUT1 mode control
OUT1 driver mode selection.
000 = CMOS, both pins active.
001 = CMOS, positive pin active, negative pin tristate.
010 = CMOS, positive pin tristate, negative pin active.
011 = CMOS, both pins tristate.
100 = LVDS.
101 = LVPECL (default).
110 = not used.
111 = not used.
[2:1]
OUT1 CMOS polarity
Selects the polarity of the OUT1 pins in CMOS mode.
00 = positive pin logic is true = 1, false = 0/negative pin logic is true = 0, false = 1 (default).
01 = positive pin logic is true = 1, false = 0/negative pin logic is true = 1, false = 0.
10 = positive pin logic is true = 0, false = 1/negative pin logic is true = 0, false = 1.
11 = positive pin logic is true = 0, false = 1/negative pin logic is true = 1, false = 0.
These bits are ineffective unless Bits[5:3] select CMOS mode.
0
Enable SPI control of OUT1
driver control
Controls OUT1 driver functionality.
0 = OUT1 is LVDS or LVPECL, per the OUTSEL pin (Pin 16) (default).
1 = OUT1 functionality defined by Bits[7:1].
Input PLL Control (Register 0x33)
Table 34.
Address
Bit
Bit Name
Description
0x33
7
Loop filter sample rate control
Select/bypass 8× clock divider to the digital loop filter.
0 = selected (default).
1 = bypassed.
6
Select 2× frequency divider
Select/bypass the 2× frequency divider.
0 = bypassed (default).
1 = selected.
Note that this bit is not functional in 19.44 MHz mode.
[5:4]
Select crystal frequency
Select the crystal frequency for 19.44 MHz mode.
00 = 52.000 MHz (default).
01 = 50.000 MHz.
10 = 49.860 MHz.
11 = 49.152 MHz.
Note that these bits are functional only in 19.44 MHz mode.
[3:0]
Unused
Unused.
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