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參數(shù)資料
| 型號： | AD9571ACPZLVD-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/20頁 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK GEN 25MHZ 40LFCSP |
| 標準包裝： | 2,500 |
| 類型： | 時鐘發(fā)生器，扇出配送，多路復(fù)用器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 156.25MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-WQ（6x6） |
| 包裝： | 帶卷 (TR) |
Ethernet Clock Generator, 10 Clock Outputs
AD9571
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for its use,norforanyinfringements ofpatents or other
rightsofthirdpartiesthat mayresult fromitsuse.Specificationssubjecttochangewithoutnotice. No
license isgranted by implication or otherwise under anypatent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2009 Analog Devices, Inc. All rights reserved.
FEATURES
Fully integrated VCO/PLL core
0.17 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz
0.41 ps rms jitter from 12 kHz to 20 MHz at 125 MHz
Input crystal or clock frequency of 25 MHz
Preset divide ratios for 156.25 MHz, 33.33 MHz,100 MHz, and
125 MHz
Choice of LVPECL or LVDS output format
Integrated loop filter
6 copies of reference clock output
Rates configured via strapping pins
Space saving 6 mm × 6 mm 40-lead LFCSP
0.48 W power dissipation (LVDS operation)
0.69 W power dissipation (LVPECL operation)
3.3 V operation
APPLICATIONS
Ethernet line cards, switches, and routers
SCSI, SATA, and PCI-express
PCI support included
Low jitter, low phase noise clock generation
FUNCTIONAL BLOCK DIAGRAM
XTAL
OSC
REFCLK
REFSEL
6 × 25MHz
CMOS
1 × 33.33MHz
2 × 100MHz OR
125MHz
1 × 156.25MHz
FORCE_LOW
CMOS
LVPECL OR
LVDS
VCO
PFD/CP
3RD-ORDER
LPF
FREQSEL
DI
V
IDE
RS
AD9571
07499-
001
Figure 1.
GENERAL DESCRIPTION
The AD9571 provides a multioutput clock generator function
comprising a dedicated PLL core that is optimized for Ethernet
line card applications. The integer-N PLL design is based on the
Analog Devices, Inc., proven portfolio of high performance, low
jitter frequency synthesizers to maximize network performance.
Other applications with demanding phase noise and jitter
requirements also benefit from this part.
The PLL section consists of a low noise phase frequency
detector (PFD), a precision charge pump (CP), a low phase
noise voltage controlled oscillator (VCO), and a preprogrammed
feedback divider and output divider. By connecting an external
crystal or reference clock to the REFCLK pin, frequencies up to
156.25 MHz can be locked to the input reference.
Each output divider and feedback divider ratio is prepro-
grammed for the required output rates. No external loop filter
components are required, thus conserving valuable design time
and board space.
The AD9571 is available in a 40-lead 6 mm × 6 mm lead frame
chip scale package and can be operated from a single 3.3 V
supply. The operating temperature range is 40°C to +85°C.
2 × OCTAL
GbE PHY
2 × OCTAL
GbE PHY
2 × OCTAL
GbE PHY
2 × OCTAL
GbE PHY
48 + 2 SWITCH/MAC
OPTIONAL
CX-4 PHY
CPU
ISLAND
AD9571
XAUI
6 × 25MHz
2 × 125MHz
1 × 156.25MHz
1 × 33.33MHz
07499-
002
Figure 2. Typical Application
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