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參數(shù)資料
| 型號： | AD9571ACPZLVD-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/20頁 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK GEN 25MHZ 40LFCSP |
| 標準包裝： | 2,500 |
| 類型： | 時鐘發(fā)生器，扇出配送，多路復用器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 156.25MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 40-LFCSP-WQ（6x6） |
| 包裝： | 帶卷 (TR) |
AD9571
Rev. 0 | Page 16 of 20
The value of the resistor is dependent on the board design and
timing requirements (typically 10 to 100 is used). CMOS
outputs are limited in terms of the capacitive load or trace
length that they can drive. Typically, trace lengths less than
6 inches are recommended to preserve signal rise/fall times
and signal integrity.
10
MICROSTRIP
GND
5pF
60.4
1.0 INCH
CMOS
07499-
015
Figure 15. Series Termination of CMOS Output
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9571 do not supply enough current
to provide a full voltage swing with a low impedance resistive,
far-end termination, as shown in Figure 16. The far-end termin-
ation network should match the PCB trace impedance and
provide the desired switching point. The reduced signal swing
may still meet receiver input requirements in some applications.
This can be useful when driving long trace lengths on less
critical nets.
50
10
VPULLUP = 3.3V
CMOS
5pF
100
100
07499-
016
Figure 16. CMOS Output with Far-End Termination
LVPECL CLOCK DISTRIBUTION
The low voltage, positive emitter-coupled logic (LVPECL)
outputs of the AD9571 provide the lowest jitter clock signals
available from the AD9571. The LVPECL outputs (because they
are open emitter) require a dc termination to bias the output
transistors. The simplified equivalent circuit in Figure 13 shows
the LVPECL output stage.
In most applications, a standard LVPECL far-end termination is
recommended, as shown in Figure 17. The resistor network is
designed to match the transmission line impedance (50) and
the desired switching threshold (1.3 V).
3.3V
LVPECL
50
50
SINGLE-ENDED
(NOT COUPLED)
3.3V
LVPECL
127
127
83
83
VT = VCC – 1.3V
07499-
017
Figure 17. LVPECL Far-End Termination
3.3V
LVPECL
DIFFERENTIAL
(COUPLED)
3.3V
LVPECL
100
0.1nF
200
200
07499-
018
Figure 18. LVPECL with Parallel Transmission Line
LVDS CLOCK DISTRIBUTION
Low voltage differential signaling (LVDS) is a second differ-
ential output option for the AD9571. LVDS uses a current mode
output stage with a factory programmed current level. The
normal value (default) for this current is 3.5 mA, which yields a
350 mV output swing across a 100 resistor. The LVDS
outputs meet or exceed all ANSI/TIA/EIA-644 specifications.
A recommended termination circuit for the LVDS outputs is
shown in Figure 19.
50
50
LVDS
100
07499-
019
Figure 19. LVDS Output Termination
See the AN-586 Application Note on the Analog Devices
website at www.analog.com for more information about LVDS.
REFERENCE INPUT
By default, the crystal oscillator is enabled and used as the
reference source, which requires the connection of an external
25 MHz crystal. The REFSEL pin is pulled high internally by
about 30 kΩ to support default operation. When REFSEL is tied
low, the crystal oscillator is powered down, and the REFCLK pin
must provide a good quality 25 MHz reference clock instead.
This single-ended input can be driven by either a dc-coupled
LVCMOS level signal or an ac-coupled sine wave or square
wave, provided that an external divider is used to bias the input
at VS/2.
Table 17. REFSEL Definition
REFSEL
Reference Source
0
REFCLK input
1
Internal crystal oscillator
POWER AND GROUNDING CONSIDERATIONS AND
POWER SUPPLY REJECTION
Many applications seek high speed and performance under
less than ideal operating conditions. In these application
circuits, the implementation and construction of the PCB is as
important as the circuit design. Proper RF techniques must be
used for device selection, placement, and routing, as well as for
power supply bypassing and grounding to ensure optimum
performance.
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