參數(shù)資料
型號(hào)： AD9572ACPZPEC-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 1/20頁(yè)
文件大?。?/td> 0K
描述： IC PLL CLOCK GEN 25MHZ 40LFCSP
標(biāo)準(zhǔn)包裝： 2,500
類型： 時(shí)鐘發(fā)生器，扇出配送，多路復(fù)用器
PLL： 是
輸入： 晶體
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 1:7
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 156.25MHz
除法器/乘法器： 是/無(wú)
電源電壓： 2.97 V ~ 3.63 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-WQ（6x6）
包裝： 帶卷 (TR)
Fiber Channel/Ethernet Clock Generator IC,
7 Clock Outputs
AD9572
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2009-2011 Analog Devices, Inc. All rights reserved.
FEATURES
Fully integrated dual VCO/PLL cores
0.22 ps rms jitter from 0.637 MHz to 10 MHz at 106.25 MHz
0.19 ps rms jitter from 1.875 MHz to 20 MHz at 156.25 MHz
0.42 ps rms jitter from 12 kHz to 20 MHz at 125 MHz
Input crystal or clock frequency of 25 MHz
Preset divide ratios for 106.25 MHz, 156.25 MHz, 33.33 MHz,
100 MHz, and 125 MHz
Choice of LVPECL or LVDS output format
Integrated loop filters
Copy of reference clock output
Rates configured via strapping pins
0.71 W power dissipation (LVDS operation)
1.07 W power dissipation (LVPECL operation)
3.3 V operation
Space saving, 6 mm × 6 mm, 40-lead LFCSP
APPLICATIONS
Fiber channel line cards, switches, and routers
Gigabit Ethernet/PCIe support included
Low jitter, low phase noise clock generation
FUNCTIONAL BLOCK DIAGRAM
XTAL
OSC
REFCLK
REFSEL
1 × 25MHz
CMOS
FREQSEL
AD9572
2 × 106.25MHz
VCO
P
F
D/
CP
LP
F
TH
IR
D
OR
D
E
R
DI
V
ID
E
R
S
LVPECL
OR LVDS
2 × 100MHz
OR 125MHz
VCO
P
F
D/
CP
LP
F
3RD
O
RDE
R
DI
V
IDE
RS
LVPECL
OR LVDS
1 × 156.25MHz
LVPECL
OR LVDS
FORCE_LOW
1 × 33.33MHz
CMOS
LDO
0
74
98
-00
1
Figure 1.
GENERAL DESCRIPTION
The AD9572 provides a multioutput clock generator function
along with two on-chip PLL cores, optimized for fiber channel
line card applications that include an Ethernet interface. The
integer-N PLL design is based on the Analog Devices, Inc.,
proven portfolio of high performance, low jitter frequency
synthesizers to maximize network performance. Other applica-
tions with demanding phase noise and jitter requirements also
benefit from this part.
The PLL section consists of a low noise phase frequency
detector (PFD), a precision charge pump (CP), a low phase
noise voltage controlled oscillator (VCO), and a preprogrammed
feedback divider and output divider. By connecting an external
crystal or reference clock to the REFCLK pin, frequencies up to
156.25 MHz can be locked to the input reference. Each output
divider and feedback divider ratio is preprogrammed for the
required output rates.
A second PLL also operates as an integer-N synthesizer and
drives two LVPECL or LVDS output buffers for 106.25 MHz
operation. No external loop filter components are required, thus
conserving valuable design time and board space.
The AD9572 is available in a 40-lead, 6 mm × 6 mm lead frame
chip scale package (LFCSP) and can be operated from a single
3.3 V supply. The temperature range is 40°C to +85°C.
QUAD SFP
PHY
QUAD SFP
PHY
QUAD SFP
PHY
QUAD SFP
PHY
16-PORT FIBRE CHANNEL ASIC
10G SFP+
CPU
ISLAND
AD9572
1 × 156.25MHz
2 × 106.25MHz
1 × 100MHz/125MHz
1 × 25MHz
1 × 33.33MHz
0
74
98-
0
02
Figure 2. Typical Application
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