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參數(shù)資料
| 型號(hào)： | AD9572ACPZPEC-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK GEN 25MHZ 40LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘發(fā)生器，扇出配送，多路復(fù)用器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:7 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 156.25MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-WQ（6x6） |
| 包裝： | 帶卷 (TR) |
AD9572
Rev. B | Page 10 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. * = SHORT TO PIN 36.
2. ** = SHORT TO PIN 14.
3. NC = NO CONNECT.
4. NOTE THAT THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL
CONNECTION AS WELL AS A THERMAL ENHANCEMENT. FOR THE DEVICE TO
FUNCTION PROPERLY, THE PADDLE MUST BE ATTACHED TO GROUND (GND).
PIN 1
INDICATOR
1
GND
2
VS
3
NC
4
25M
5
VS
6
XO
7
XO
8
REFCLK
9
REFSEL
10
GND
23 33M
24 VS
25 VS
26 VS
27 FREQSEL
28 VS
29 106M
30 106M
22 100M/125M
21 100M/125M
11
V
S
12
**
13
**
15
V
S
17
15
6M
16
V
S
18
15
6M
19
10
0M
/1
25
M
20
10
0M
/1
25
M
14
B
Y
P
A
S
2
33
V
S
34
G
N
D
35
V
S
36
B
Y
P
A
S
1
37
F
O
R
C
E
_L
O
W
38
*
39
V
S
40
V
S
32
10
6M
31
10
6M
TOP VIEW
(Not to Scale)
AD9572
0
749
8-
0
07
Figure 6. Pin Configuration
Pin No.
Mnemonic
Description
1, 10, 34
GND
Ground. Includes external paddle (EPAD).
2
VS
Power Supply Connection for the 25M CMOS Buffer.
3
NC
No Connect. This pin should be left floating.
4
25M
CMOS 25 MHz Output.
5
VS
Power Supply Connection for the Crystal Oscillator.
6, 7
XO
External 25 MHz Crystal.
8
REFCLK
25 MHz Reference Clock Input. Tie low when not in use.
9
REFSEL
Logic Input. Used to select the reference source.
11
VS
Power Supply Connection for the GbE PLL.
12, 13
N/A
Short to Pin 14.
14, 36
BYPASS2, BYPASS1
These pins are for bypassing each LDO to ground with a 220 nF capacitor.
15
VS
Power Supply Connection for the GbE VCO.
16
VS
Power Supply Connection for the 156M LVDS Output Buffer and Output Dividers.
17
156M
LVPECL/LVDS Output at 156.25 MHz.
18
156M
Complementary LVPECL/LVDS Output at 156.25 MHz.
19, 21
100M/125M
LVPECL/LVDS Output at 100 MHz or 125 MHz. Selected by FREQSEL pin strapping.
20, 22
100M/125M
Complementary LVPECL/LVDS Output at 100 MHz or 125 MHz.
23
33M
CMOS 33.33 MHz Output.
24
VS
Power Supply Connection for the 33M CMOS Output Buffer and Output Dividers.
25
VS
Power Supply Connection for the 100M/125M LVDS Output Buffer and Output Dividers.
26
VS
Power Supply Connection for the GbE PLL Feedback Divider.
27
FREQSEL
Logic Input. Used to configure output drivers.
28
VS
Power Supply Connection for the FC PLL Feedback Divider.
29, 31
106M
LVPECL/LVDS Output at 106.25 MHz.
30, 32
106M
Complementary LVPECL/LVDS Output at 106.25 MHz.
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