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參數(shù)資料
| 型號： | AD9572ACPZPEC-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK GEN 25MHZ 40LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時鐘發(fā)生器，扇出配送，多路復(fù)用器 |
| PLL： | 是 |
| 輸入： | 晶體 |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:7 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 156.25MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-WQ（6x6） |
| 包裝： | 帶卷 (TR) |
AD9572
Rev. B | Page 16 of 20
THEORY OF OPERATION
XTAL
OSC
REFCLK
REFSEL
VS
GND
BYPASS1
1
0
AD9572
DIVIDE
BY 5
DIVIDE
BY 4
DIVIDE
BY 5
DIVIDE
BY 3
33M
FORCE_LOW
CMOS
33.33MHz
0
1
0
125MHz/100MHz
LVPECL/
LVDS
100M/125M
125MHz/100MHz
LVPECL/
LVDS
25M
CMOS
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
DIVIDE
BY 17
DIVIDE
BY 5
DIVIDE
BY 4
VLDO
VCO
106M
LVPECL/
LVDS
106.25MHz
106M
LDO
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
DIVIDE
BY 25
DIVIDE
BY 4
DIVIDE
BY 4
VLDO
VCO
LDO
156M
156.25MHz
LVPECL/
LVDS
BYPASS2
07
49
8-
0
13
LEVEL
DECODE
FREQSEL
Figure 17. Detailed Block Diagram
Figure 17 shows a block diagram of the AD9572. The chip
combines dual PLL cores, which are configured to generate the
specific clock frequencies required for networking applications
without any user programming. This PLL is based on proven
Analog Devices synthesizer technology, noted for its exceptional
phase noise performance. The AD9572 is highly integrated and
includes loop filters, regulators for supply noise immunity, all
the necessary dividers with multiple output buffers in a choice
of formats, and a crystal oscillator. A user need only supply a
25 MHz reference clock or an external crystal to implement an
entire line card clocking solution that does not require any
processor intervention. A copy of the 25 MHz reference source
is also available.
OUTPUTS
Table 14 provides a summary of the outputs available.
Table 14. Output Formats
Frequency
Format
Copies
25 MHz
CMOS
1
106.25 MHz
LVPECL/LVDS
2
156.25 MHz
LVPECL/LVDS
1
100 MHz or 125 MHz
LVPECL/LVDS
2
33.33 MHz
CMOS
1
Note that the pins labeled 100M/125M can provide 100 MHz or
125 MHz by strapping the FREQSEL pin as shown in Table 15.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD9572-EVALZ-LVD | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs |
| AD9572-EVALZ-PEC | 制造商:AD 制造商全稱:Analog Devices 功能描述:Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs |
| AD9572XCPZLVD | 制造商:Analog Devices 功能描述: |
| AD9572XCPZPEC | 制造商:Analog Devices 功能描述: |
| AD9573 | 制造商:AD 制造商全稱:Analog Devices 功能描述:PCI-Express Clock Generator IC, PLL Core, Dividers, Two Outputs |
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