參數(shù)資料
型號(hào): AD9575ARUZLVD
廠商: Analog Devices Inc
文件頁數(shù): 15/16頁
文件大?。?/td> 0K
描述: IC PLL CLOCK GEN 25MHZ 16TSSOP
標(biāo)準(zhǔn)包裝: 96
系列: PCI Express® (PCIe)
類型: 扇出緩沖器(分配),網(wǎng)絡(luò)時(shí)鐘發(fā)生器
PLL:
主要目的: PCI Express(PCIe)
輸入: 晶體
輸出: LVCMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 312.5MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
AD9575
Rev. A | Page 8 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
VDDA
VDDX
XO1
GNDA
GNDX
XO2
GNDA
VDDA
16
15
14
13
12
11
10
9
GND
LVDS/LVPECL OUT
CMOS OUT/SEL1
GND_CMOS
VDD_CMOS
VDD
SEL0
AD9575
TOP VIEW
(Not to Scale)
08
46
2-
0
05
Figure 4. Pin Configuration
Table 11. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 7
GNDA
Analog Ground.
2, 8
VDDA
Analog Power Supply (3.3 V).
3
VDDX
Crystal Oscillator Power Supply.
4, 5
XO1, XO2
External Crystal.
6
GNDX
Crystal Oscillator Ground.
9
GND_CMOS
Ground for LVCMOS Output.
10
CMOS OUT/SEL1
LVCMOS Output/Output Frequency Select.
11
VDD_CMOS
Power Supply for LVCMOS Output.
12
VDD
Power Supply for LVDS or LVPECL Output.
13
LVDS/LVPECL OUT
Complementary LVDS or LVPECL Output.
14
LVDS/LVPECL OUT
LVDS or LVPECL Output.
15
GND
Ground for LVDS or LVPECL Output.
16
SEL0
Output Frequency Select.
Table 12. Output Frequency Selection1
Mode
XTAL
SEL0
LVDS/LVPECL Output
LVCMOS Output
1
25 MHz
GND
100 MHz
33.33 MHz
2
25 MHz
VS
GND
156.25 MHz
High-Z
3
25.78125 MHz
VS
161.13 MHz
High-Z
4
25 MHz
No connect
125 MHz
62.5 MHz
5
25 MHz
15 kΩ pull-up
VS
159.375 MHz
High-Z
6
25 MHz
15 kΩ pull-up
GND
312.5 MHz
High-Z
7
25 MHz
VS
106.25 MHz
High-Z
8
19.44 MHz
VS
No connect
155.52 MHz
High-Z
1 The AD9575 must be power-cycled if the select pin voltages are altered.
2 X = in Mode 1, Pin 10 is configured as an LVCMOS output (33.33 MHz) by forcing Pin 16 to GND. In Mode 4, Pin 10 is configured as an LVCMOS output (62.5 MHz) by
leaving Pin 16 unconnected.
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