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參數(shù)資料
| 型號： | AD9575ARUZLVD |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK GEN 25MHZ 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 系列： | PCI Express® (PCIe) |
| 類型： | 扇出緩沖器（分配），網(wǎng)絡(luò)時鐘發(fā)生器 |
| PLL： | 是 |
| 主要目的： | PCI Express（PCIe） |
| 輸入： | 晶體 |
| 輸出： | LVCMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 312.5MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
AD9575
Rev. A | Page 12 of 16
THEORY OF OPERATION
XTAL
OSC
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
1/n
1/k
SEL
LVCMOS
CMOS OUT/SEL1
VDDX
GNDX
VDDA
GNDA
VDD_CMOS
GND_CMOS
SEL0
1/m
VLDO
2.488GHz TO
2.55GHz VCO
LVDS
100MHz
AD9575
08
46
2-
0
1
5
LDO
LVDS/LVPECL OUT
Figure 17. Detailed Block Diagram
Figure 17 shows a block diagram of the AD9575. The chip features
a PLL core, which is configured to generate the specific clock
frequencies via pin programming. By appropriate connection of
the select pins, SEL0 and SEL1, the divide ratios of the feedback
divider (n), LVDS output divider (m), and LVCMOS output
divider (k) can be programmed (see Table 12). In Mode 1 and
Mode 4, Pin 10 is configured as an LVCMOS output by forcing
Pin 16 to GND (33.33 MHz output) or by leaving Pin 16 uncon-
nected (62.5 MHz output). In conjunction with a band-select
VCO that operates over the range of 2.488 GHz to 2.55 GHz,
a wide range of popular network reference frequencies can
be generated. This PLL is based on proven Analog Devices
synthesizer technology, noted for its exceptional phase noise
performance. The AD9575 is highly integrated and includes
the loop filter, a regulator for supply noise immunity, all the
necessary dividers, output buffers, and a crystal oscillator. A
user need only supply an external crystal to implement a
clocking solution that requires no processor intervention.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the reference clock and feedback
divider to produce an output proportional to the phase and
frequency difference between them. Figure 18 shows a
simplified schematic.
0
846
2-
0
16
D1
Q1
CLR1
REFCLK
HIGH
UP
D2
Q2
CLR2
HIGH
DOWN
CP
CHARGE
PUMP
VP
GND
FEEDBACK
DIVIDER
Figure 18. PFD Simplified Schematic
POWER SUPPLY
The AD9575 requires a 3.3 V ± 10% power supply for VS. The
Specifications section gives the performance expected from the
AD9575 with the power supply voltage within this range. The
absolute maximum range of 0.3 V to +3.6 V, with respect to
GND, must never be exceeded on the VDD, VDDA, VDDX,
and VDD_CMOS pins.
Good engineering practice should be followed in the layout
of power supply traces and the ground plane of the PCB. The
power supply should be bypassed on the PCB with adequate
capacitance (>10 μF). The AD9575 should be bypassed with
adequate capacitors (0.1 μF) at all power pins as close as possible
to the part. The layout of the AD9575 evaluation board is a
good example.
LVPECL CLOCK DISTRIBUTION
Because they are open emitter, the LVPECL outputs require
a dc termination to bias the output transistors. The simplified
equivalent circuit in Figure 19 shows the LVPECL output stage.
08
46
2-
02
6
LVPECL
VTERM
LVPECL
50
50
50
50
0.1F
200
200
Figure 19. LVPECL AC-Coupled Termination
In most applications, a standard LVPECL far-end termination is
recommended, as shown in Figure 20. The resistor network is
designed to match the transmission line impedance (50 Ω) and
the desired switching threshold (1.3 V).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9575ARUZPEC | 功能描述:IC PLL CLOCK GEN 25MHZ 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:PCI Express® (PCIe) 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| AD9575-EVALZ-LVD | 制造商:AD 制造商全稱:Analog Devices 功能描述:Network Clock Generator, Two Outputs |
| AD9575-EVALZ-PEC | 制造商:AD 制造商全稱:Analog Devices 功能描述:Network Clock Generator, Two Outputs |
| AD9576/PCBZ | 功能描述:DUAL CHANNEL ASYNCHRONOUS EVALUA 制造商:analog devices inc. 系列:* 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:1 |
| AD9576BCPZ | 功能描述:DUAL CHANNEL ASYNCHRONOUS CLOCK 制造商:analog devices inc. 系列:* 零件狀態(tài):有效 標(biāo)準(zhǔn)包裝:1 |
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