參數(shù)資料
型號(hào)： AD9577BCPZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/44頁(yè)
文件大小： 0K
描述： IC CLK GEN PLL DUAL 40LFCSP
標(biāo)準(zhǔn)包裝： 2,500
系列： PCI Express® (PCIe)
類型： 扇出緩沖器（分配），網(wǎng)絡(luò)時(shí)鐘發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，PCI Express（PCIe），SONET/SDH
輸入： 時(shí)鐘，晶體
輸出： LVCMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:5
差分 - 輸入:輸出： 無(wú)/是
頻率 - 最大： 637.5MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 40-WFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-WQ（6x6）
包裝： 帶卷 (TR)
AD9577
Data Sheet
Rev. 0 | Page 30 of 44
OUTPUT CHANNEL DIVIDERS
Between each VCO and its associated chip outputs, there are
two divider stages: a VCO divider that has a divide ratio between
2 and 6 and an output divider that can be set to divide between
1 and 32. This cascade of dividers allows a minimum output
channel divide ratio of 2 and a maximum of 192. With VCO
frequencies ranging between 2.15 GHz and 2.55 GHz, the part
can be programmed to spot frequencies over a continuous
frequency range of from 11.2 MHz to 200 MHz, and it can be
programmed to spot frequencies over a continuous frequency
range of 200 MHz and 637.5 MHz, with only a few small gaps.
Table 19. Divider Ratio Setting Registers
Divider
I2C Registers
Parameter
Divide
Range
Channel 0 VCO divider
ADV0[7:5]
V0
2 to 6
Channel 1 VCO divider
ADV1[7:5]
V1
2 to 6
Channel 2 VCO divider
BDV0[7:5]
V2
2 to 6
Channel 3 VCO divider
BDV1[7:5]
V3
2 to 6
Channel 0 output divider
ADV0[4:0]
D0
Channel 1 output divider
ADV1[4:0]
D1
Channel 2 output divider
BDV0[4:0]
D2
Channel 3 output divider
BDV1[4:0]
D3
1 Set to 00000 for divide by 32.
Asserting the SyncCh01 or SyncCh23 bits (Register ADV2[0]
or Register BDV2[0]) allows each PLL output channel to use a
common VCO divider. This feature allows the OUT0/OUT1 and
OUT2/OUT3 output ports to have minimal skew when their
relative output channel divide ratio is an integer multiple.
Duty-cycle correction circuitry ensures that the output duty cycle
remains at 50%.
V0[2:0]
D0[4:0]
OUT0
OUTPUT
DIVIDER
VCO
DIVIDER
V1[2:0]
D1[4:0]
OUT1
OUTPUT
DIVIDER
VCO
DIVIDER
VCO
V2[2:0]
D2[4:0]
OUT2
OUTPUT
DIVIDER
VCO
DIVIDER
V3[2:0]
D3[4:0]
OUT3
OUTPUT
DIVIDER
VCO
DIVIDER
VCO
09
28
4-
0
39
Figure 35. Output Channel Divider Signal Path
OUTPUTS
Each output port can be individually configured as either
differential LVPECL, differential LVDS, or two single-ended
LVCMOS clock outputs. The simplified equivalent circuit of the
LVDS outputs is shown in Figure 36.
3.5mA
OUTxP
OUTxN
09
284
-04
0
Figure 36. LVDS Outputs Simplified Equivalent Circuit
The simplified equivalent circuit of the LVPECL outputs is
shown in Figure 37.
3.3V
OUTxP
OUTxN
GND
092
84-
0
41
Figure 37. LVPECL Outputs Simplified Equivalent Circuit
Output channels (consisting of a VCO divider, output divider, and
an output buffer) can be individually powered down to save power.
Setting PDCH0, PDCH1, PDCH2, and PDCH3 (Register BP0[1:0]
and Register DR1[7:6]) powers down the appropriate channel.
Output buffer combinations of LVDS, LVPECL, and CMOS can be
selected by setting DR1[5:0] as is shown in Table 20 and Table 21.
Table 20. PLL1 Output Driver Format Control Bits,
Register DR1[2:0]
FORMAT1 (PLL1)
Register DR1[2:0]
OUT1P/OUT1N
OUT0P/OUT0N
000
LVPECL
001
LVDS
010
2 × CMOS
LVPECL
011
2 × CMOS
100
2 × CMOS
LVDS
101
LVPECL
LVDS
110
LVPECL
2 × CMOS
2 × CMOS
1 This indicates that the CMOS outputs are in phase; otherwise, they are in
antiphase.
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