參數(shù)資料
型號(hào): AD9640-125EBZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 33/52頁(yè)
文件大?。?/td> 0K
描述: ADC 14BIT 125MSPS DUAL 64-LFCSP
設(shè)計(jì)資源: Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
AD9640 Eval Brd Family Gerber Files
AD9640 Eval Brd BOM
AD9640 Eval Brd Schematic
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 2
位數(shù): 14
采樣率(每秒): 125M
數(shù)據(jù)接口: 串行
輸入范圍: 2 Vpp
在以下條件下的電源(標(biāo)準(zhǔn)): 910mW @ 125MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9640
已供物品:
AD9640
Rev. B | Page 39 of 52
CHANNEL/CHIP SYNCHRONIZATION
The AD9640 has a SYNC input that allows the user flexible
synchronization options for synchronizing the internal blocks.
The clock divider sync feature is useful to guarantee synchronized
sample clocks across multiple ADCs. The signal monitor block
can also be synchronized using the SYNC input allowing properties
of the input signal to be measured during a specific time period.
The input clock divider can be enabled to synchronize on a single
occurrence of the sync signal or on every occurrence. The signal
monitor block is synchronized on every SYNC input signal.
The SYNC input is internally synchronized to the sample clock;
however, to ensure there is no timing uncertainty between multiple
parts, the SYNC input signal should be externally synchronized to
the input clock signal, meeting the setup and hold times shown
in Table 8. The SYNC input should be driven using a single-
ended CMOS-type signal.
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