參數(shù)資料
型號(hào)： AD9640-125EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 41/52頁(yè)
文件大?。?/td> 0K
描述： ADC 14BIT 125MSPS DUAL 64-LFCSP
設(shè)計(jì)資源： Interfacing ADL5534 to AD9640 High Speed ADC (CN0049)
AD9640 Eval Brd Family Gerber Files
AD9640 Eval Brd BOM
AD9640 Eval Brd Schematic
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 2
位數(shù)： 14
采樣率（每秒）： 125M
數(shù)據(jù)接口： 串行
輸入范圍： 2 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 910mW @ 125MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9640
已供物品： 板
AD9640
Rev. B | Page 46 of 52
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
0x11A
Signal Monitor
Result
Channel B
Register 1
(Global)
Signal Monitor Result Channel B[15:8]
Read only
0x11B
Signal Monitor
Result
Channel B
Register 2
(Global)
Open
Signal Monitor Result Channel B[19:16]
Read only
MEMORY MAP REGISTER DESCRIPTION
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x100)
Bit 7—Signal Monitor Sync Enable
Bit 7 enables the sync pulse from the external SYNC input to
the signal monitor block. The sync signal is passed when Bit 7
is high and Bit 0 is high. This is continuous sync mode.
Bits[6:3]—Reserved
Bit 2—Clock Divider Next Sync Only
If the sync enable bit (Address 0x100[0]) is high and the clock
divider sync enable (Address 0x100[1]) is high, Bit 2 allows the
clock divider to sync to the first sync pulse it receives and ignore
the rest. Address 0x100[1] resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
passed when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
Bit 0—Master Sync Enable
Bit 0 must be high to enable any of the sync functions.
Fast Detect Control (Register 0x104)
Bits[7:4]—Reserved
Bits[3:1]—Fast Detect Mode Select
These bits set the mode of the fast detect output bits according
Bit 0—Fast Detect Enable
Bit 0 is used to enable the fast detect bits. When the fast detect
outputs are disabled, the outputs go into a high impedance state.
In LVDS mode, when the outputs are interleaved, the outputs go
high-Z only if both channels are turned off (power-down/standby/
output disabled). If only one channel is turned off (power-down/
standby/output disabled), the fast detect outputs repeat the data
of the active channel.
Fine Upper Threshold (Register 0x106 and Register 0x107)
Register 0x106, Bits[7:0]—Fine Upper Threshold[7:0]
Register 0x107, Bits[7:5]—Reserved
Register 0x107, Bits[4:0]—Fine Upper Threshold[12:8]
These registers provide the fine upper limit threshold. This 13-bit
value is compared to the 13-bit magnitude from the ADC block
and, if the ADC magnitude exceeds this threshold value, the
F_UT flag is set.
Fine Lower Threshold (Register 0x108 and Register 0x109)
Register 0x108, Bits[7:0]—Fine Lower Threshold
[7:0]
Register 0x109, Bits[7:5]—Reserved
Register 0x109, Bits[4:0]—Fine Lower Threshold[12:8]
These registers provide a fine lower limit threshold. This 13-bit
value is compared to the 13-bit magnitude from the ADC block
and, if the ADC magnitude is less than this threshold value, the
F_LT flag is set.
Signal Monitor DC Correction Control (Register 0x10C)
Bit 7—Reserved
Bit 6—DC Correction Freeze
When Bit 6 is set high, the dc correction is no longer updated
to the signal monitoring block. It holds the last dc value it
calculated.
Bits[5:2]—DC Correction Bandwidth
These bits set the averaging time of the signal monitor dc correc-
tion function. It is a 4-bit word that sets the bandwidth of the
correction block (see Table 26).
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