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參數(shù)資料
| 型號： | AD9644-155KITZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL FOR AD9644 |
| 設(shè)計資源： | AD9644 Gerber Files |
| 標準包裝： | 1 |
| 系列： | * |
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AD9644
Data Sheet
Rev. C | Page 22 of 44
AD8376
AD9644
1H
1nF
VPOS
VCM
15pF
68nH
301
165
5.1pF
3.9pF
180nH
1000pF
NOTES
1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS
WITH THE EXCEPTION OF THE 1H CHOKE INDUCTORS (0603LS).
180nH
220nH
09180-
115
Figure 52. Differential Input Configuration Using the AD8376 (Filter Values Shown Are for a 20 MHz Bandwidth Filter Centered at 140 MHz)
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9644.
The input full scale range can be adjusted through the SPI port by
adjusting Bit 0 through Bit 4 of Register 0x18. These bits can be
used to change the full scale between 1.383 V p-p and 2.087 V p-p
in 0.022 V steps, as shown in Table 17.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9644 sample clock inputs,
CLK+ and CLK, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK pins by
means of a transformer or a passive component configuration.
These pins are biased internally (see Figure 53) and require no
external bias. If the inputs are floated, the CLK pin is pulled low
to prevent inadvertent clocking.
AVDD
CLK+
2pF
CLK–
0.9V
09180-
044
Figure 53. Equivalent Clock Input Circuit
Clock Input Options
The AD9644 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of
the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section. The
minimum conversion rate of the AD9644 is 40 MSPS. At clock
rates below 40 MSPS, dynamic performance of the AD9644 can
degrade.
Figure 54 and Figure 55 show two preferred methods for clocking
the AD9644 (at clock rates up to 640 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 640 MHz, and the RF transformer is recom-
mended for clock frequencies from 40 MHz to 200 MHz. The
back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the AD9644 to
approximately 0.8 V p-p differential.
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9644 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.
0.1F
SCHOTTKY
DIODES:
HSMS2822
CLOCK
INPUT
50
100
CLK–
CLK+
ADC
Mini-Circuits
ADT1-1WT, 1:1Z
XFMR
09180-
048
Figure 54. Transformer-Coupled Differential Clock (Up to 200 MHz)
0.1F
1nF
CLOCK
INPUT
1nF
50
CLK–
CLK+
SCHOTTKY
DIODES:
HSMS2822
ADC
09180-
049
Figure 55. Balun-Coupled Differential Clock (Up to 640 MHz)
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
/AD9522 clock drivers offer excellent jitter performance.
100
0.1F
240
PECL DRIVER
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
AD95xx
ADC
09180-
Figure 56. Differential PECL Sample Clock (Up to 640 MHz)
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