參數(shù)資料
型號： AD9644-155KITZ
廠商： Analog Devices Inc
文件頁數(shù)： 28/44頁
文件大?。?/td> 0K
描述： KIT EVAL FOR AD9644
設計資源： AD9644 Gerber Files
標準包裝： 1
系列： *
AD9644
Data Sheet
Rev. C | Page 34 of 44
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17. Memory Map Registers
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default/
Comments
Chip Configuration Registers
0x00
SPI port
configuration
(global)1
0
LSB first
Soft reset
1
Soft reset
LSB first
0
0x18
Nibbles are
mirrored so
that LSB-first
or MSB-first
mode is set
correctly,
regardless of
shift mode.
To control
this register,
all channel
index bits in
Register
0x05 must
be set.
0x01
Chip ID
(global)
8-bit chip ID[7:0]
(AD9644 = 0x7E)
(default)
0x7E
Read only
0x02
Chip grade
(global)
Open
Speed grade ID
00 = 80 MSPS
10 = 155 MSPS
Open
Speed grade
ID
differentiates
devices;
read only
Channel Index and Transfer Registers
0x05
Channel index
(global)
Open
ADC B and
Link B
(default)
ADC A and
Link A
(default)
0x03
Bits set to
determine
which
device on
the chip
receives
next write
command;
local
registers
only
0xFF
Transfer
(global)
Open
Transfer
0x00
Synchro-
nously
transfers
data from
master shift
register to
slave
ADC Functions
0x08
Power modes
(local)
Open
External power-
down pin
function (local)
0 = power-
down
1 = standby
Open
Internal power-down mode
(local)
00 = normal operation
01 = full power-down
10 = standby
11 = reserved
0x00
Determines
various
generic
modes of
chip
operation
0x09
Global clock
(global)
Open
Duty cycle
stabilizer
(default)
0x01
0x0A
PLL status
(global)
PLL
Locked
Open
0x00
Read Only
0x0B
Clock divide
(global)
Open
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
0x00
Clock divide
values other
than 000
automatically
causes duty
cycle
stabilizer to
become
active
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