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參數(shù)資料
| 型號： | AD9644-155KITZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL FOR AD9644 |
| 設(shè)計(jì)資源： | AD9644 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
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Data Sheet
AD9644
Rev. C | Page 39 of 44
JESD204A Link Control Register 1 (Register 0x60)
Bit 7—Reserved
Bit 6—Serial Tail Bit Enable
If this bit is set, the unused tail bits are padded with a pseudo
random number sequence from a 31-bit LFSR (see JESD204A
5.1.4).
Bit 5—Serial Test Sample Enable
If this bit is set, JESD204A test samples are enabled—transport
layer test sample sequence (as specified in JESD204A section
5.1.6.2) is sent on all link lanes.
Bit 4—Serial Lane Synchronization Enable
If this bit is set, lane synchronization is enabled. Both sides
perform lane sync. Frame alignment character insertion uses
either /K28.3/ or /K28.7/ control characters (see JESD204A
5.3.3.4).
Bits[3:2]—Serial Lane Alignment Sequence Mode
00: initial lane alignment sequence disabled.
01: initial lane alignment sequence enabled.
10: reserved.
11: initial lane alignment sequence always on test mode—
JESD204A data link layer test mode where repeated lane alignment
sequence is sent on all lanes.
Bit 1—Frame Alignment Character Insertion Disable
If Bit 1 is set, the frame alignment character insertion is
disabled per JESD204A section 5.3.3.4.
Bit 0—Serial Transmit Link Powered Down
If Bit 0 is set high, the serial transmit link is held in reset with its
clock gated off. The JESD204A transmitter should be powered
down when changing any of the link configuration bits.
JESD204A Link Control Register 2 (Register 0x61)
Bits[7:6]—Local DSYNC Mode
00: individual/separate mode. Each link is controlled by a
separate DSYNC pin that independently controls code group
synchronization.
01: global mode. Any DSYNC signal causes the link to begin
code group synchronization.
10: sync active mode. DSYNC signal is active—force code group
synchronization.
11: DSYNC pin disabled.
Bit 5—DSYNC Pin Input Inverted
If this bit is set, the DSYNC pin of the link is inverted (active high).
Bit 4—CMOS DSYNC Input
0: LVDS differential pair DSYNC input (default)
1: CMOS single ended DSYNC input
Bit 3—Open
Bit 2—Bypass 8b/10b Encoding
If this bit is set the 8b/10b encoding is bypassed and the most
significant bits are set to 0.
Bit 1—Invert Transmit Bits
Setting this bit inverts the 10 serial output bits. This effectively
inverts the output signals.
Bit 0—Mirror Serial Output Bits
Setting this bit reverses the order of the 10b outputs.
JESD204A Link Control Register 3 (Register 0x62)
Bit 7—Disable CHKSUM
Setting this bit high disables the CHKSUM configuration
parameter (for testing purposes only).
Bit 6—Open
Bits[5:4]—Link Test Generation Input Selection
00: 16-bit test generation data injected at sample input to
the link.
01: 10-bit test generation data injected at output of 8b/10b
encoder (at input to PHY).
10: reserved.
11: reserved.
Bit 3—Open
Bits[2:0]—Link Test Generation Mode
000: normal operation (test mode disabled).
001: alternating checker board.
010: 1/0 word toggle.
011: PN sequence—long.
100: PN sequence—short.
101: continuous/repeat user test mode—most significant bits
from user pattern (1, 2, 3, 4) placed on the output for 1 clock
cycle and then repeat. (output user pattern 1, 2, 3, 4, 1, 2, 3, 4, 1,
2, 3, 4…).
110: single user test mode—most significant bits from user
pattern (1, 2, 3, 4) placed on the output for 1 clock cycle and
then output all zeros. (output user pattern 1, 2, 3, 4, then output
all zeros).
111: ramp output.
JESD204A Link Control Register 4 (Register 0x63)
Bits[7:0]—Initial Lane Alignment Sequence Repeat Count
Specifies the number of times the initial lane alignment
sequence (ILAS) is repeated. If 0 is programmed the ILAS does
not repeat. If 1 is programmed the ILAS repeat one time and so
on. See Register 0x60, Bits[3:2] to enable the ILAS and for a test
mode to continuously enable the initial lane alignment
sequence.
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