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參數(shù)資料
| 型號(hào)： | AD9644-80KITZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9644 |
| 設(shè)計(jì)資源： | AD9644 Gerber Files AD9644 80KITZ BOM |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 1.4 ~ 2.1 Vpp |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | * |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9644 |
| 已供物品： | 板 |
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Data Sheet
AD9644
Rev. C | Page 23 of 44
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 57. The AD9510/
performance.
100
0.1F
50k
CLK–
CLK+
CLOCK
INPUT
CLOCK
INPUT
AD95xx
LVDS DRIVER
ADC
09
180
-051
Figure 57. Differential LVDS Sample Clock (Up to 640 MHz)
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applica-
tions, the CLK+ pin should be driven directly from a CMOS gate,
and the CLK pin should be bypassed to ground with a 0.1 μF
capacitor (see Figure 58).
OPTIONAL
100
0.1F
501
150 RESISTOR IS OPTIONAL.
CLK–
CLK+
VCC
1k
CLOCK
INPUT
AD95xx
CMOS DRIVER
ADC
0
9180-
052
Figure 58. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
Input Clock Divider
The AD9644 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. For
divide ratios other than 1 the duty cycle stabilizer is automatically
enabled.
The AD9644 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state. This synchro-
nization feature allows multiple parts to have their clock dividers
aligned to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. The AD9644 requires a tight
tolerance on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9644 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows the user to provide
a wide range of clock input duty cycles without affecting the perfor-
mance of the AD9644. Noise and distortion performance are
nearly flat for a wide range of duty cycles with the DCS enabled.
Jitter in the rising edge of the input is still of paramount concern
and is not easily reduced by the internal stabilization circuit. The
loop has a time constant associated with it that must be considered
in applications in which the clock rate can change dynamically.
A wait time of 1.5 μs to 5 μs is required after a dynamic clock
frequency increase or decrease before the DCS loop is relocked to
the input signal. During the time period that the loop is not locked,
the DCS loop is bypassed, and internal device timing is dependent
on the duty cycle of the input clock signal. In such applications, it
may be appropriate to disable the duty cycle stabilizer. In all other
applications, enabling the DCS circuit is recommended to
maximize ac performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. For inputs near full scale, the degradation in
SNR from the low frequency SNR (SNRLF) at a given input
frequency (fINPUT) due to jitter (tJRMS) can be calculated by
SNRHF = 10 log[(2π × fINPUT × tJRMS)2 + 10
)
10
/
(
LF
SNR
]
In the equation, the rms aperture jitter represents the clock input
jitter specification. IF undersampling applications are particularly
sensitive to jitter, as illustrated in Figure 59. The measured curve in
Figure 59 was taken using an ADC clock source with approxi-
mately 65 fs of jitter, which combines with the 125 fs of jitter
inherent in the AD9644 to produce the result shown.
50
55
60
65
70
75
1
10
100
1000
S
N
R
(
d
BF
S
)
INPUT FREQUENCY (MHz)
0.05ps
0.2ps
0.5ps
1ps
1.5ps
MEASURED
09
18
0-
04
3
Figure 59. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9644.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type of
source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
Refer to the AN-501 Application Note and the AN-756 Application
Note (visit www.analog.com) for more information about jitter
performance as it relates to ADCs.
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