參數(shù)資料
型號: AD9644-80KITZ
廠商: Analog Devices Inc
文件頁數(shù): 3/44頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR AD9644
設(shè)計資源: AD9644 Gerber Files
AD9644 80KITZ BOM
標準包裝: 1
ADC 的數(shù)量: 2
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 串行
輸入范圍: 1.4 ~ 2.1 Vpp
在以下條件下的電源(標準): *
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD9644
已供物品:
Data Sheet
AD9644
Rev. C | Page 11 of 44
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
VCMA
DNC
4
PDWN
5
DNC
6
CSB
7
SCLK
4
2
D
S
Y
N
C
+
A
3
2
D
S
Y
N
C
–A
2
D
R
V
D
1
2
D
R
G
N
D
02
D
O
U
T
+
A
91
D
O
U
T
–A
81
D
O
U
T
+
B
71
D
O
U
T
–B
61
D
R
G
N
D
51
D
R
V
D
41
D
S
Y
N
C
+
B
31
D
S
Y
N
C
–B
44
A
V
D
54
V
IN
+
B
64
V
IN
–B
74
A
V
D
84
A
V
D
3
4
A
V
D
2
4
A
V
D
14
A
V
D
0
4
V
IN
+
A
93
V
IN
–A
8
3
A
V
D
73
A
V
D
TOP
VIEW
(Not to Scale)
AD9644
25
26
DRVDD
DNC
27
DRGND
28
AVDD
29
SYNC
30
AVDD
31
CLK–
32
CLK+
33
AVDD
34
DNC
35
AVDD
36
VCMB
8
SDIO
9
DRVDD
10
DRVDD
11
DRGND
12
DNC
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD
MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
0
918
0-
1
04
Figure 4. LFCSP Pin Configuration (Top View)
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
ADC Power Supplies
11, 15, 22, 27, 28
DRVDD
Supply
Digital Output Driver Supply (1.8 V Nominal).
2, 4, 7, 9, 37, 38, 41,
42, 43, 44, 47, 48
AVDD
Supply
Analog Power Supply (1.8 V Nominal).
3, 12, 25, 32, 34, 35
DNC
Do Not Connect.
10, 16, 21, 26
DRGND
Driver
Ground
Digital Driver Supply Ground.
0
AGND,
Exposed Pad
Ground
The exposed thermal pad on the bottom of the package provides the analog
ground for the part. This exposed pad must be connected to ground for
proper operation.
ADC Analog
40
VIN+A
Input
Differential Analog Input Pin (+) for Channel A.
39
VINA
Input
Differential Analog Input Pin () for Channel A.
45
VIN+B
Input
Differential Analog Input Pin (+) for Channel B.
46
VINB
Input
Differential Analog Input Pin () for Channel B.
36
VCMA
Output
Common-Mode Level Bias Output for Channel A Analog Input.
1
VCMB
Output
Common-Mode Level Bias Output for Channel B Analog Input.
5
CLK+
Input
ADC Clock Input—True.
6
CLK
Input
ADC Clock Input—Complement.
Digital Input
8
SYNC
Input
Input Clock Divider Synchronization Pin.
24
DSYNC+A
Input
Active Low JESD204A LVDS Channel A SYNC Input—True/JESD204A CMOS
Channel A SYNC Input.
23
DSYNCA
Input
Active Low JESD204A LVDS Channel A SYNC Input—Complement.
14
DSYNC+B
Input
Active Low JESD204A LVDS Channel B SYNC Input—True/JESD204A CMOS
Channel A SYNC Input.
13
DSYNCB
Input
Active Low JESD204A LVDS Channel B SYNC Input—Complement.
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