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參數(shù)資料
| 型號： | AD9644-80KITZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9644 |
| 設計資源： | AD9644 Gerber Files AD9644 80KITZ BOM |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 80M |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 1.4 ~ 2.1 Vpp |
| 在以下條件下的電源（標準）： | * |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9644 |
| 已供物品： | 板 |
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Data Sheet
AD9644
Rev. C | Page 27 of 44
Table 11. AD9644 JESD204A Frame Alignment Monitoring and Correction Replacement Characters
Scrambling
Lane Synchronization
Character to be Replaced
Last Octet in
Multiframe
Replacement Character
Off
On
Last octet in frame repeated from previous frame
No
K28.7 (0xFC)
Off
On
Last octet in frame repeated from previous frame
Yes
K28.3 (0x7C)
Off
Last octet in frame repeated from previous frame
Not applicable
K28.7 (0xFC)
On
Last octet in frame equals D28.7 (0xFC)
No
K28.7 (0xFC)
On
Last octet in frame equals D28.3 (0x7C)
Yes
K28.3 (0x7C)
On
Off
Last octet in frame equals D28.7 (0x7C)
Not applicable
K28.7 (0xFC)
Frame and Lane Alignment Monitoring and Correction
Frame alignment monitoring and correction is part of the
JESD204A specification. The 14-bit word requires two octets to
transmit all the data. The two octets (MSB and LSB), where
F = 2, make up a frame. During normal operating conditions
frame alignment is monitored via alignment characters, which
are inserted under certain conditions at the end of a frame.
Table 11 summarizes the conditions for character insertion
along with the expected characters under the various operation
modes. If lane synchronization is enabled, the replacement
character value depends on whether the octet is at the end of a
frame or at the end of a multiframe.
Based on the operating mode, the receiver can ensure that it is
still synchronized to the frame boundary by correctly receiving
the replacement characters.
Digital Outputs and Timing
The AD9644 has differential digital outputs that power up
by default. The driver current is derived on chip and sets the
output current at each output equal to a nominal 4 mA. Each
output presents a 100 Ω dynamic internal termination to reduce
unwanted reflections.
A 100 Ω differential termination resistor should be placed at
each receiver input to result in a nominal 400 mV peak-to-peak
swing at the receiver (see Figure 66). Alternatively, single-ended
50 Ω termina-tion can be used. When single-ended termination
is used, the termination voltage should be DRVDD/2; otherwise,
ac coupling capacitors can be used to terminate to any single-
ended voltage.
The AD9644 digital outputs can interface with custom ASICs
and FPGA receivers, providing superior switching performance
in noisy environments. Single point-to-point network topologies
are recommended with a single differential 100 Ω termination
resistor placed as close to the receiver logic as possible. The
common mode of the digital output automatically biases itself
to half the supply of the receiver (that is, the common-mode
voltage is 0.9 V for a receiver supply of 1.8 V) if dc-coupled
connecting is used (see Figure 67). For receiver logic that is not
within the bounds of the DRVDD supply, an ac-coupled
connection should be used. Simply place a 0.1 μF capacitor on
each output pin and derive a 100 Ω differential termination
close to the receiver side.
If there is no far-end receiver termination or if there is poor
differential trace routing, timing errors may result. To avoid
such timing errors, it is recommended that the trace length be
less than six inches and that the differential output traces be
close together and at equal lengths.
100
OR
100
DIFFERENTIAL
TRACE PAIR
DOUT+x
DRVDD
VRXCM
DOUT–x
VCM = Rx VCM
OUTPUT SWING = 400mV p-p
0.1F
RECEIVER
09
18
0-
09
3
Figure 66. AC-Coupled Digital Output Termination Example
100
DIFFERENTIAL
TRACE PAIR
DOUT+x
DRVDD
DOUT–x
VCM = DRVDD/2
OUTPUT SWING = 400mV p-p
RECEIVER
09
18
0-
0
92
Figure 67. DC-Coupled Digital Output Termination Example
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