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參數(shù)資料
| 型號： | AD9717BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/80頁 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 14BIT LO PWR 40LFCSP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 系列： | TxDAC® |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 86mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 4 電流，單極 |
| 采樣率（每秒）： | 125M |
| 產(chǎn)品目錄頁面： | 785 (CN2011-ZH PDF) |
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AD9714/AD9715/AD9716/AD9717
Rev. A | Page 32 of 80
THEORY OF OPERATION
I DAC
Q DAC
AUX1DAC
AUX2DAC
BAND
GAP
CLOCK
DIST
10k
QRSET
16k
IRSET
16k
IREF
100A
IRCML
1k TO
250
QRCML
1k TO
250
500
SPI
INTERFACE
1 INTO 2
INTERLEAVED
DATA
INTERFACE
I DATA
Q DATA
1.8V
LDO
1V
AD9717
07
26
5-
0
46
RLIN
IOUTN
IOUTP
RLIP
AVDD
AVSS
RLQP
QOUTP
QOUTN
RLQN
DB11
DB10
DB9
DB8
DVDDIO
DVSS
DVDD
DB7
DB6
DB5
DB
12
DB
13
(
M
S
B
)
SD
IO
/F
O
R
M
A
T
S
C
LK
/C
LK
M
D
R
ESE
T
/PI
N
M
D
RE
F
IO
F
S
AD
JI
/AUX
I
FS
A
D
JQ
/A
U
X
Q
CM
L
I
DB4
DB3
DB2
DB1
DB
0(
L
S
B
)
DC
L
K
IO
CV
D
CL
KI
N
C
VSS
CM
L
Q
C
S
/P
W
R
D
N
Figure 84. Simplified Block Diagram
Figure 84 shows a simplified block diagram of the AD9714/
AD9715/AD9716/AD9717 that consists of two DACs, digital
control logic, and a full-scale output current control. Each DAC
contains a PMOS current source array capable of providing a
nominal full-scale current (IxOUTFS) of 2 mA and a maximum of
4 mA. The arrays are divided into 31 equal currents that make
up the five most significant bits (MSBs). The next four bits, or
middle bits, consist of 15 equal current sources whose value is
1/16 of an MSB current source. The remaining LSBs are binary
weighted fractions of the current sources of the middle bits.
Implementing the middle and lower bits with current sources,
instead of an R-2R ladder, enhances its dynamic performance
for multitone or low amplitude signals and helps maintain the
high output impedance of the DACs (that is, >200 MΩ).
All of these current sources are switched to one or the other
of the two output nodes (IOUTP or IOUTN) via PMOS differential
current switches. The switches are based on the architecture that
was pioneered in the AD976x family, with further refinements
to reduce distortion contributed by the switching transient. This
switch architecture also reduces various timing errors and
provides matching complementary drive signals to the inputs
of the differential current switches.
The analog and digital I/O sections of the AD9714/AD9715/
AD9716/AD9717 have separate power supply inputs (AVDD and
DVDDIO) that can operate independently over a 1.8 V to 3.3 V
range. The core digital section requires 1.8 V. An optional on-chip
LDO is provided for DVDDIO supplies greater than 1.8 V, or the
1.8 V can be supplied directly through DVDD. A 1.0 μF bypass
capacitor at DVDD (Pin 7) is required when using the LDO.
The core is capable of operating at a rate of up to 125 MSPS. It
consists of edge-triggered latches and the segment decoding logic
circuitry. The analog section includes PMOS current sources,
associated differential switches, a 1.0 V band gap voltage
reference, and a reference control amplifier.
Each DAC full-scale output current is regulated by the reference
control amplifier and can be set from 1 mA to 4 mA via an external
resistor, xRSET, connected to its full-scale adjust pin (FSADJx).
The external resistor, in combination with both the reference
control amplifier and voltage reference, VREFIO, sets the reference
current, IxREF, which is replicated to the segmented current sources
with the proper scaling factor. The full-scale current, IxOUTFS, is
32 × IxREF.
Optional on-chip xRSET resistors are provided that can be pro-
grammed between a nominal value of 8 kΩ to 32 kΩ (4 mA to
1 mA IxOUTFS, respectively).
The AD9714/AD9715/AD9716/AD9717 provide the option of
setting the output common mode to a value other than AVSS
via the output common-mode pins (CMLI and CMLQ). This
facilitates directly interfacing the output of the AD9714/AD9715/
AD9716/AD9717 to components that require common-mode
levels greater than 0 V.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9717BCPZ | 制造商:Analog Devices 功能描述:IC DAC 14BIT 125MSPS LFCSP-40 |
| AD9717BCPZRL7 | 功能描述:IC DAC DUAL 14BIT LO PWR 40LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC® 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9717-DPG2-EBZ | 功能描述:ADC 14BIT DUAL 40LFCSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9717-EBZ | 制造商:Analog Devices 功能描述:DUAL 14B, LOW POWER D-A CONVERTER - Boxed Product (Development Kits) |
| AD9720BN | 制造商:Rochester Electronics LLC 功能描述:10BIT 400MSPS DAC IC IC - Bulk |
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